AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 7

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL
PROPAGATION DELAY, t
OUTPUT SKEW, LVPECL OUTPUTS
LVDS
PROPAGATION DELAY, t
OUTPUT SKEW, LVDS OUTPUTS
CMOS
PROPAGATION DELAY, t
OUTPUT SKEW, CMOS OUTPUTS
DELAY ADJUST
1
2
3
4
5
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Corresponding CMOS drivers set to A for noninverting and B for inverting.
The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.
Incremental delay; does not include propagation delay.
All delays between zero scale and full scale can be estimated by linear interpolation.
Output Rise Time, t
Output Fall Time, t
High Frequency Clock Distribution Configuration
Clock Distribution Configuration
Variation with Temperature
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
Output Rise Time, t
Output Fall Time, t
For All Divide Values
Variation with Temperature
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
Output Rise Time, t
Output Fall Time, t
For All Divide Values
Variation with Temperature
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
Shortest Delay Range
Longest Delay Range
Delay Variation with Temperature
All LVDS Outputs Across Multiple Parts
All CMOS Outputs Across Multiple Parts
Zero Scale
Full Scale
Zero Scale
Full Scale
Short Delay Range
Long Delay Range
Quarter Scale
Zero Scale
Full Scale
Zero Scale
Full Scale
3
FP
FL
FC
RP
RL
RC
5
5
4
PECL
LVDS
CMOS
4
, CLK-TO-LVPECL OUTPUT
, CLK-TO-LVDS OUTPUT
, CLK-TO-CMOS OUTPUT
1
1
1
Min
835
773
1.4
1.6
50
540
200
1.72
5.7
Rev. B | Page 7 of 80
Typ
70
70
995
933
0.8
5
13
170
160
1.8
1.25
6
25
495
475
2.1
2.6
4
28
315
880
570
2.31
8.0
0.23
−0.02
0.3
0.24
Max
180
180
1180
1090
15
40
220
350
350
2.1
62
150
430
1000
985
2.6
66
180
675
680
1180
950
2.89
10.1
Unit
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ns
ps/°C
ps
ps
ps
ps
ps
ns
ps/°C
ps
ps
ps
ps
ps
ps
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
Test Conditions/Comments
Termination = 50 Ω to V
20% to 80%, measured differentially
80% to 20%, measured differentially
See
See
Termination = 100 Ω differential; 3.5 mA
20% to 80%, measured differentially
20% to 80%, measured differentially
Delay off on all outputs
Delay off on all outputs
Termination = open
20% to 80%; C
80% to 20%; C
Fine delay off
Fine delay off
LVDS and CMOS
Register 0x0A1 (0x0A4) (0x0A7) (0x0AA) [5:0] 101111b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 000000b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 101111b
Register 0x0A1 (0x0A4) (0x0A7) (0x0AA) [5:0] 000000b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 000000b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 001100b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 101111b
Figure 42
Figure 44
LOAD
LOAD
= 10 pF
= 10 pF
S
− 2 V; level = 810 mV
AD9517-4
2
2