Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 29

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

Z80 CPU
User’s Manual
9
IORQ
Input/Output Request (output, active Low, tristate). IORQ indicates that
the lower half of the address bus holds a valid I/O address for an I/O read or
write operation. IORQ is also generated concurrently with M1 during an
interrupt acknowledge cycle to indicate that an interrupt response vector can
be placed on the data bus.
M1
Machine Cycle One (output, active Low). M1, together with MREQ,
indicates that the current machine cycle is the opcode fetch cycle of an
instruction execution. M1 together with IORQ, indicates an interrupt
acknowledge cycle.
MREQ
Memory Request (output, active Low, tristate). MREQ indicates that the
address bus holds a valid address for a memory read of memory write
operation.
NMI
Non-Maskable Interrupt (input, negative edge-triggered). NMI has a
higher priority than INT. NMI is always recognized at the end of the current
instruction, independent of the status of the interrupt enable flip-flop, and
automatically forces the CPU to restart at location
.
0066H
RD
Read (output, active Low, tristate). RD indicates that the CPU wants to
read data from memory or an I/O device. The addressed I/O device or
memory should use this signal to gate data onto the CPU data bus.
RESET
Reset (input, active Low). RESET initializes the CPU as follows: it resets
the interrupt enable flip-flop, clears the PC and registers I and R, and sets the
UM008005-0205
Overview