Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 89

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

UM008005-0205
Address
N, N+1
N+2 to N+9
N+10,N+11
N + 12
JUMP JP
JUMP JR
JUMP JP
CALL
Decrement B, Jump
If Non Zero DJNZ
Return RE
Return From
INT RETI
Return From
Non Maskable
INT RETN
Table 16. Jump, Call, and Return Group
The instruction
byte, relative jump instruction decrements the B register and the jump
occurs if the B register has not been decremented to zero. The relative
displacement is expressed as a signed two’s complement number. A
simple example of its use is:
IMMED.
EXT.
RELATIVE
Register
INDIR.
IMMED.
EXT.
RELATIVE
REGISTER
INDIR.
Instruction
LD B, 7
(Perform a sequence of instructions)
DJNZ -8
(Next Instruction)
DJNZ
nn
PC+e
(HL)
(IX)
(IY)
nn
PC+e
(SP)
(SP+1)
is used to facilitate program loop control. This two
Condition
Un-
Cond.
C3
n
n
18
e-2
EB
DD
E9
FD
E9
CD
n
n
C9
ED
4D
ED
45
Carry Non
D8
n
n
38
e-2
DC
n
n
D8
Carry
D2
n
n
30
e-2
D4
n
n
D0
Zero
CA
n
n
28
e-2
CC
n
n
C8
Z80 CPU Instruction Description
Comments
: set B register to count of 7
: loop to be performed 7 times
: to jump from N+12 to N+2
Non
Zero
C2
n
n
20
e-2
C4
n
n
C0
Parity
Even
EA
n
n
EC
n
n
E8
Parity
Odd
E2
n
n
E4
n
n
E0
User’s Manual
Sign
Neg
FA
n
n
FC
n
n
F8
Z80 CPU
Sign
Pos
F2
n
n
F4
n
n
F0
Reg
B≠0
10
e-2
69