CP82C54Z Intersil, CP82C54Z Datasheet - Page 11

• Manufacturer Part Number: CP82C54Z
• Description: IC TIMER PROG CMOS 8MHZ 24-PDIP
• Manufacturer: Intersil
• Type: Programmable Timerr

Specifications of CP82C54Z

• Frequency: 8MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MODE DEFINITIONS
The following are defined for use in describing the operation
of the 82C54.
CLK PULSE - A rising edge, then a falling edge, in that
order, of a Counter’s CLK input.
TRIGGER - A rising edge of a Counter’s Gate input.
COUNTER LOADING - The transfer of a count from the CR
to the CE (See “Functional Description”)
CS
D7
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
FIGURE 8. READ/WRITE OPERATIONS SUMMARY
RD
D6
1
1
1
1
0
0
0
0
X
1
1
1
1
1
1
1
WR
X
D5
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
COMMANDS
A1
0
0
1
1
0
0
1
1
X
X
D4
0
0
0
1
0
0
A0
X
X
0
1
0
1
0
1
0
1
D3
0
0
1
1
0
0
11
Write into Counter 0
Write into Counter 1
Write into Counter 2
Write Control Word
Read from Counter 0
Read from Counter 1
Read from Counter 2
No-Operation (Three-State)
No-Operation (Three-State)
No-Operation (Three-State)
D2
0
1
1
0
1
0
D1
1
0
0
0
0
1
FIGURE 7. READ-BACK COMMAND EXAMPLE
D0
0
0
0
0
0
0
Read-Back Count and Status of Counter 0
Read-Back Status of Counter 1
Read-Back Status of Counters 2, 1
Read-Back Count of Counter 2
Read-Back Count and Status of Counter 1
Read-Back Status of Counter 1
82C54
DESCRIPTION
MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is typically used for event counting. After the Control
Word is written, OUT is initially low, and will remain low until
the Counter reaches zero. OUT then goes high and remains
high until a new count or a new Mode 0 Control Word is
written to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 CLK
pulses after the initial count is written.
If a new count is written to the Counter it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
pulses after the new count of N is written.
1. Writing the first byte disables counting. Out is set low
2. Writing the second byte allows the new count to be
immediately (no clock pulse required).
loaded on the next CLK pulse.
Count and Status Latched for Counter 0
Status Latched for Counter 1
Status Latched for Counter 2,
But Not Counter 1
Count Latched for Counter 2
Count Latched for Counter 1,
But Not Status
Command Ignored, Status Already
Latched for Counter 1
RESULT