MAX1181ECM+D Maxim Integrated Products, MAX1181ECM+D Datasheet - Page 12

IC ADC 10BIT 80MSPS DUAL 48-TQFP

MAX1181ECM+D

Manufacturer Part Number
MAX1181ECM+D
Description
IC ADC 10BIT 80MSPS DUAL 48-TQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1181ECM+D

Number Of Bits
10
Sampling Rate (per Second)
80M
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
291mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
five clock cycle latency between any particular sample
and its corresponding output data. The output coding
can be chosen to be either straight offset binary or two’s
complement (Table 1) controlled by a single pin (T/B).
Pull T/B low to select offset binary and high to activate
two’s complement output coding. The capacitive load
on the digital outputs D0A–D9A and D0B–D9B should
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Figure 2. MAX1181 T/H Amplifiers
12
______________________________________________________________________________________
INA+
INA-
INB+
INB-
S4a
S4b
S4a
S4b
S4c
S4c
C2a
C2b
C2a
C2b
INTERNAL
S2a
INTERNAL
INTERNAL
S2a
INTERNAL
BIAS
BIAS
BIAS
BIAS
S1
S1
S2b
S2b
C1a
C1b
C1a
C1b
COM
COM
COM
COM
S5a
S5b
S5a
S5b
S3a
S3b
S3a
S3b
be kept as low as possible (< 15pF), to avoid large digi-
tal currents that could feed back into the analog portion
of the MAX1181, thereby degrading its dynamic perfor-
mance. Using buffers on the digital outputs of the ADCs
can further isolate the digital outputs from heavy capaci-
tive loads. To further improve the dynamic performance
OUT
OUT
OUT
OUT
HOLD
TRACK
HOLD
TRACK
MAX1181
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS

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