MAX1181ECM+D Maxim Integrated Products, MAX1181ECM+D Datasheet - Page 13

• Manufacturer Part Number: MAX1181ECM+D
• Description: IC ADC 10BIT 80MSPS DUAL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1181ECM+D

• Number Of Bits: 10
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 291mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3. System Timing Diagram
Table 1. MAX1181 Output Codes For Differential Inputs
*V
of the MAX1181 small-series resistors (e.g., 100Ω), add
to the digital output paths, close to the MAX1181.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wake-up and data output valid.
The MAX1181 offers two power-save modes; sleep and
full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled) and current consumption is reduced to
2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
______________________________________________________________________________________________________
REF
DIFFERENTIAL INPUT
ANALOG INPUT
= V
DATA OUTPUT
DATA OUTPUT
CLOCK INPUT
-V
-V
V
with Internal Reference and Parallel Outputs
-V
V
REF ✕
REF ✕
VOLTAGE*
REF ✕
REFP
D9A–D0A
D9B–D0B
REF ✕
REF ✕
0
511/512
- V
511/512
512/512
1/512
1/512
REFN
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
Power-Down (PD) and Sleep
t
D0
N - 6
N - 6
DIFFERENTIAL INPUT
- FULL SCALE + 1 LSB
+FULL SCALE - 1LSB
N
(SLEEP) Modes
- FULL SCALE
N - 5
N - 5
Bipolar Zero
+ 1 LSB
- 1 LSB
t
CLK
N + 1
N - 4
N - 4
5 CLOCK-CYCLE LATENCY
N + 2
t
CH
N - 3
N - 3
value prior to the power-down. Pulling OE high, forces
the digital outputs into a high-impedance state.
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers. The user
may select the R
ter performance to suit a particular application. For the
application in Figure 5, a R
the capacitive load to prevent ringing and oscillation.
STRAIGHT OFFSET
N + 3
11 1111 1111
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
N - 2
N - 2
BINARY
T/B = 0
t
CL
Applications Information
N + 4
ISO
N - 1
N - 1
and C
DD
/ 2 output voltage for level-
IN
ISO
N + 5
values to optimize the fil-
TWO’S COMPLEMENT
of 50Ω is placed before
N
N
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
N + 6
T/B = 1
N + 1
N + 1
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