LTC1272-8CCSW#PBF Linear Technology, LTC1272-8CCSW#PBF Datasheet - Page 15

• Manufacturer Part Number: LTC1272-8CCSW#PBF
• Description: IC A/D CONV 12BIT SAMPLNG 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1272-8CCSW#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 75mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs
First Read
Second Read
Third Read
ROM Mode, Two Byte READ
As previously mentioned for a two byte read, only data
outputs D7 . . . D0/8 are used. Conversion is started in the
normal way with a Read operation and the data output
status is the same as the ROM Mode, Parallel Read. See
Figure 17 timing diagram and Table 5 data bus status. Two
more Read operations are required to access the new
conversion result. A delay equal to the LTC1272 conver-
sion time must be allowed between conversion start and
the second data Read operation. The second Read opera-
tion, with HBEN high, disables conversion start and places
the high byte (4 MSBs) on data outputs D3/11 . . . DO18.
A third read operation accesses the low data byte (DB7
appear on data outputs D11 . . . D8 during all three read
operations above.
. . . DB0) and starts another conversion. The 4 MSB’s
PPLICATI
TRACK
HOLD
HBEN
BUSY
DATA
RD
RD
CS
O
DB7
Low
DB7
U
D7
S
t
8
I FOR ATIO
t
U
1
t
t
3
2
DB6
Low
DB6
D6
t
OLD DATA
4
DB7-DB0
t
12
Figure 17. ROM Mode, Two Byte Read Timing Diagram
W
t
t
7
5
t
t
CONV
9
DB5
Low
DB5
D5
U
t
8
t
1
DB4
DB4
Low
D4
t
3
Microprocessor Interfacing
The LTC1272 is designed to interface with microproces-
sors as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
The HBEN input serves as a data byte select for 8-bit
processors and is normally connected to the micropro-
cessor address bus.
MC68000 Microprocessor
Figure 18 shows a typical interface for the MC68000. The
LTC1272 is operating in the Slow Memory Mode. Assum-
ing the LTC1272 is located at address C000, then the
following single 16-bit Move instruction both starts a
conversion and reads the conversion result:
NEW DATA
t
DB11-DB8
4
Move.W $C000,D0
D3/11
DB11
t
DB3
DB3
t
5
7
t
9
t
11
t
10
t
8
D2/10
DB10
DB2
DB2
t
1
t
t
3
2
NEW DATA
t
DB7-DB0
4
t
12
D1/9
DB1
DB9
DB1
t
t
5
7
LTC1272 • TA19
t
9
LTC1272
D0/8
DB0
DB8
DB0
15
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