LTC2234IUK Linear Technology, LTC2234IUK Datasheet - Page 13

• Manufacturer Part Number: LTC2234IUK
• Description: IC ADC 10BIT 135MSPS SAMPL 48QFN
• Manufacturer: Linear Technology

Specifications of LTC2234IUK

• Number Of Bits: 10
• Sampling Rate (per Second): 135M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 680mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
CONVERTER OPERATION
As shown in Figure 1, the LTC2234 is a CMOS pipelined
multistep converter. The converter has five pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The encode input is differen-
tial for improved common mode noise immunity. The
LTC2234 has two phases of operation, determined by the
state of the differential ENC
the text will refer to ENC
and ENC
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
+
less than ENC
U
+
–
U
greater than ENC
as ENC low.
+
/ENC
–
input pins. For brevity,
W
–
as ENC high
U
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2234
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (C
ENC
ENC
A
A
IN
IN
+
–
+
–
LTC2234
15Ω
15Ω
1.6V
1.6V
Figure 2. Equivalent Input Circuit
6k
V
V
6k
DD
DD
V
DD
C
1pF
C
1pF
PARASITIC
PARASITIC
LTC2234
SAMPLE
C
C
SAMPLE
SAMPLE
1.6pF
1.6pF
) through
2234 F02
13
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