LTC2234IUK Linear Technology, LTC2234IUK Datasheet - Page 17

• Manufacturer Part Number: LTC2234IUK
• Description: IC ADC 10BIT 135MSPS SAMPL 48QFN
• Manufacturer: Linear Technology

Specifications of LTC2234IUK

• Number Of Bits: 10
• Sampling Rate (per Second): 135M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 680mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CLOCK
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 1.7dB. See the Typical Performance Charac-
teristics section.
Driving the Encode Inputs
The noise performance of the LTC2234 can depend on the
encode signal quality as much as on the analog input. The
ENC
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
APPLICATIO S I FOR ATIO
INPUT
+
/ENC
0.1µF
50Ω
–
Figure 11. Transformer Driven ENC
inputs are intended to be driven differentially,
1:4
ENC –
ENC
+
U
LTC2234
V
V
DD
DD
1.6V BIAS
1.6V BIAS
U
6k
6k
V
DD
W
+
/ENC
ADC CIRCUITS
TO INTERNAL
–
U
2234 F11
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to V
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2234 is 135Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 3.5ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC
input. The falling edge of ENC
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 30% to 70% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3V
resistors.
The lower limit of the LTC2234 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2234 is 1Msps.
DD
for single-ended drive.
DD
+
is ignored and the internal
+
or 2/3V
pin to sample the analog
DD
LTC2234
using external
17
2234fa