PIC10F220-E/OT Microchip Technology, PIC10F220-E/OT Datasheet - Page 13

• Manufacturer Part Number: PIC10F220-E/OT
• Description: 384B Flash, 16B RAM, 4 I/O, 8bit ADC 6 SOT-23 BAG
• Manufacturer: Microchip Technology
• Series: PIC® 10Fr

Specifications of PIC10F220-E/OT

• Processor Series: PIC10F
• Core: RISC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 B
• Data Ram Size: 16 B
• Interface Type: RS-232, USB
• Maximum Clock Frequency: 8 MHZ
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Operating Temperature Range: - 40 C to + 125 C
• Processor To Be Evaluated: PIC10F220
• Supply Current (max): 100 nA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: -
• Peripherals: POR, WDT
• Number Of I /o: 4
• Eeprom Size: -
• Ram Size: 16 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

3.1
The clock is internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. Internally, the PC is incremented every Q1,
and the instruction is fetched from program memory
and latched into the Instruction Register (IR) in Q4. It is
decoded and executed during Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
FIGURE 3-2:
EXAMPLE 3-1:
© 2007 Microchip Technology Inc.
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
4. BSF
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
Clocking Scheme/Instruction
Cycle
SUB_1
GPIO, BIT1
OSC1
PC
Q1
Q2
Q3
Q4
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC - 1)
Fetch INST (PC)
Q2
Fetch 1
PC
Q3
Execute 1
Q4
Fetch 2
Q1
Execute INST (PC)
Fetch INST (PC + 1)
Execute 2
Q2
Fetch 3
PC + 1
3.2
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO) then two cycles
are required to complete the instruction (Example 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3
and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
Q1
PIC10F220/222
Fetch SUB_1 Execute SUB_1
Execute INST (PC + 1)
Fetch INST (PC + 2)
Q2
Flush
PC + 2
Q3
Q4
DS41270E-page 11
Internal
phase
clock