PIC10F220-E/OT Microchip Technology, PIC10F220-E/OT Datasheet - Page 27

• Manufacturer Part Number: PIC10F220-E/OT
• Description: 384B Flash, 16B RAM, 4 I/O, 8bit ADC 6 SOT-23 BAG
• Manufacturer: Microchip Technology
• Series: PIC® 10Fr

Specifications of PIC10F220-E/OT

• Processor Series: PIC10F
• Core: RISC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 B
• Data Ram Size: 16 B
• Interface Type: RS-232, USB
• Maximum Clock Frequency: 8 MHZ
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-6
• Operating Temperature Range: - 40 C to + 125 C
• Processor To Be Evaluated: PIC10F220
• Supply Current (max): 100 nA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: -
• Peripherals: POR, WDT
• Number Of I /o: 4
• Eeprom Size: -
• Ram Size: 16 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

6.0
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
FIGURE 6-2:
© 2007 Microchip Technology Inc.
PC
(Program
Counter)
Instruction
Timer0
Instruction
Executed
Fetch
- Edge select for external clock
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
GP2/T0CKI
TMR0 MODULE AND TMR0
REGISTER
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
Pin
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0SE
T0
PC-1
F
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
OSC
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
/4
PC
T0CS
0
1
Write TMR0
executed
T0 + 2
(1)
PC + 1
PS2, PS1, PS0
Programmable
Prescaler
Read TMR0
reads NT0
3
PC + 2
(2)
(1)
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge. Restric-
tions on the external clock input are discussed in detail
in Section 6.1 “Using Timer0 With An External
Clock”.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, 1:256
are selectable. Section 6.2 “Prescaler” details the
operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
PSA
NT0
Read TMR0
reads NT0
1
0
PC + 3
(1)
PS
OUT
(2 T
Sync with
Internal
Read TMR0
reads NT0
Clocks
CY
PIC10F220/222
PC + 4
delay)
PS
Sync
NT0 + 1
Read TMR0
reads NT0 + 1
OUT
PC + 5
TMR0 Reg
Data Bus
DS41270E-page 25
Read TMR0
reads NT0 + 2
NT0 + 2
8
PC + 6