K4H561638H-ZPB3 Samsung Semiconductor, K4H561638H-ZPB3 Datasheet - Page 4

• Manufacturer Part Number: K4H561638H-ZPB3
• Manufacturer: Samsung Semiconductor

Specifications of K4H561638H-ZPB3

• Lead Free Status / Rohs Status: Compliant

1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
K4H561638H
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
•
• Maximum burst refresh cycle : 8
• 66pin TSOP II, 60Ball FBGA
Support Industrial Temp (-40 to 85°C)
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H561638H-UI/PCC
K4H561638H-UI/PB3
K4H561638H-UI/PB0
K4H561638H-ZI/PB3
K4H561638H-ZI/PB0
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Part No.
Pb-Free(RoHS compliant)
B3(DDR333@CL=2.5)
16M x 16
16M x 16
Org.
133MHz
166MHz
2.5-3-3
-
CC(DDR400@CL=3.0)
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
Max Freq.
package
A2(DDR266@CL=2.0)
133MHz
133MHz
2-3-3
-
Industrial
Interface
SSTL2
SSTL2
Rev. 1.3 February 2007
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
2.5-3-3
66pin TSOP II
-
Package
60 FBGA