K4H561638H-ZPB3 Samsung Semiconductor, K4H561638H-ZPB3 Datasheet - Page 8

• Manufacturer Part Number: K4H561638H-ZPB3
• Manufacturer: Samsung Semiconductor

Specifications of K4H561638H-ZPB3

• Lead Free Status / Rohs Status: Compliant

7.0 Input/Output Function Description
K4H561638H
RAS, CAS, WE
LDQS,(U)DQS
LDM,(UDM)
SYMBOL
BA0, BA1
A [0 : 12]
CK, CK
VDDQ
VSSQ
VREF
VDD
CKE
VSS
DQ
NC
CS
Supply
Supply
Supply
Supply
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
-
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE Low provides PRECHARGE POWER-
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughput READ and WRITE accesses. Input buffers, excluding CK,
CK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled
during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS Low level after
Vdd is applied upon 1st power up, After V
tialization sequence, it must be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH entry and exit, V
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data
on DQ8~DQ15. DM may be driven high, low, or floating during READs.
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15.
LDQS is NC on x4 and x8.
No Connect : No internal electrical connection is present.
DQ Power Supply : +2.5V ± 0.2V. (+2.6V ±0.1V for DDR400)
DQ Ground.
Power Supply : +2.5V ± 0.2V. (+2.6V ±0.1V for DDR400)
Ground.
SSTL_2 reference voltage.
DESCRIPTION
REF
REF
must be maintained to this input.
has become stable during the power on and ini-
Industrial
Rev. 1.3 February 2007
DDR SDRAM