MT41J256M8HX-125:D Micron Technology Inc, MT41J256M8HX-125:D Datasheet - Page 110

• Manufacturer Part Number: MT41J256M8HX-125:D
• Description: MICMT41J256M8HX-125:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-125:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 185mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Compliant

Mode Registers
Figure 49: MRS-to-MRS Command Timing (
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Notes:
Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the MODE REGISTER
SET (MRS) command during initialization, and it retains the stored information (except
for MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or
until the device loses power.
Contents of a mode register can be altered by reexecuting the MRS command. If the user
chooses to modify only a subset of the mode register’s variables, all variables must be
programmed when the MRS command is issued. Reprogramming the mode register will
not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or reissued) when all banks are idle and in the
precharged state (
command has been issued, two parameters must be satisfied:
The controller must wait
Figure 49).
Command
1. Prior to issuing the MRS command, all banks must be idle and precharged,
2.
3. CKE must be registered HIGH from the MRS command until
4. For a CAS latency change,
The controller must also wait
(excluding NOP and DES), as shown in Figure 50 on page 111. The DRAM requires
in order to update the requested features, with the exception of DLL RESET, which
requires additional time. Until
assumed unavailable.
Address
be satisfied, and no data bursts can be in progress.
t
Down Mode” on page 153).
MRD specifies the MRS-to-MRS command minimum cycle time.
CKE 3
CK#
CK
MRS 1
Valid
T0
t
RP is satisfied and no data bursts are in progress). After an MRS
t
MRD)
t
MRD before initiating any subsequent MRS commands (see
NOP
T1
t
XPDLL timing must be met before any nonMRS command.
110
t
MOD before initiating any nonMRS commands
t
MOD has been satisfied, the updated features are to be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
T2
t MRD
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
Ta0
Indicates a Break in
Time Scale
t
MRSPDEN (MIN) (see “Power-
t
©2006 Micron Technology, Inc. All rights reserved.
MRD and
NOP
Ta1
t
t
RP (MIN) must
MOD.
Operations
Don’t Care
MRS 2
Valid
Ta2
t
MOD