MT41J256M8HX-125:D Micron Technology Inc, MT41J256M8HX-125:D Datasheet - Page 148

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MT41J256M8HX-125:D

Manufacturer Part Number
MT41J256M8HX-125:D
Description
MICMT41J256M8HX-125:D 2GB DDR3 SDRAM
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Datasheets

Specifications of MT41J256M8HX-125:D

Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
185mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
800MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT41J256M8HX-125:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT41J256M8HX-125:D
Manufacturer:
MICRON/美光
Quantity:
20 000
Figure 90:
Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
DQ BC4
DQ BL8
CK#
CK#
CK
CK
WRITE
WRITE
Valid
Valid
T0
T0
WRITE (BL8) to PRECHARGE
NOP
NOP
T1
T1
Notes:
Notes:
NOP
NOP
T2
T2
1. DI n = data-in from column n.
2. Seven subsequent elements of data-in are applied in the programmed order following
3. Shown for WL = 7 (AL = 0, CWL = 7).
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. The write recovery time (
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
DO n.
times.
write data is shown at T7.
command can be issued to the same bank.
NOP
NOP
T3
T3
WL = AL + CWL
WL = AL + CWL
NOP
NOP
T4
T4
NOP
NOP
T5
T5
NOP
NOP
T6
T6
t
WR) is referenced from the first rising clock edge after the last
t
WR specifies the last burst WRITE cycle until the PRECHARGE
148
NOP
NOP
T7
T7
DI
DI
n
n
n + 1
n + 1
DI
DI
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n + 2
n + 2
NOP
NOP
T8
T8
DI
DI
n + 3
n + 3
DI
DI
NOP
n + 4
NOP
T9
T9
DI
2Gb: x4, x8, x16 DDR3 SDRAM
n + 5
DI
Indicates a Break in
Time Scale
Indicates a Break in
Time Scale
T10
NOP
n + 6
T10
NOP
DI
n + 7
DI
T11
NOP
T11
NOP
©2006 Micron Technology, Inc. All rights reserved.
t WR
Transitioning Data
Transitioning Data
NOP
NOP
T12
T12
t WR
Operations
NOP
NOP
Ta0
Ta0
Don’t Care
Don’t Care
Valid
Valid
Ta1
Ta1
PRE
PRE

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