K4S643232H-UC60 Samsung Semiconductor, K4S643232H-UC60 Datasheet - Page 22

• Manufacturer Part Number: K4S643232H-UC60
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S643232H-UC60

• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Device Operation &
Timing Diagram
8. Burst Stop & Interrupted by Precharge
9. MRS
*Note : 1. t
1) Normal Write (BL=4)
3) Read Interrupted by Precharge (BL=4)
1) Mode Register Set
2. t
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : All banks precharge if necessary.
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency
Read or write burst stop command is valid at every burst length.
MRS can be issued only at all banks precharge state.
DQ(CL2)
DQ(CL3)
RDL
BDL
CMD
DQM
CMD
CMD
: 1 CLK ; Last data in to burst stop delay.
CLK
CLK
CLK
: 1 CLK
DQ
PRE
WR
RD
D
0
Note 4
D
1
tRP
PRE
D
Q
2
0
tRDL
MRS
D
Q
Q
Note 1,5
3
1
0
Note 3
1
2CLK
PRE
Q
1
2
ACT
- 22
2) Write Burst Stop (BL=8)
4) Read Burst Stop (BL=4)
DQ(CL2)
DQ(CL3)
CMD
DQM
CMD
CLK
CLK
DQ
WR
RD
D
0
D
1
STOP
Rev. 1.2 April 2006
D
Q
2
0
D
Q
Q
3
1
0
x32 SDRAM
tBDL
1
STOP
D
Q
Note 2
4
1
2
D
5