K4S643232H-UC60 Samsung Semiconductor, K4S643232H-UC60 Datasheet - Page 24

• Manufacturer Part Number: K4S643232H-UC60
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S643232H-UC60

• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Device Operation &
Timing Diagram
12. About Burst Type Control
13. About Burst Length Control
Random
Random
Interrupt
Special
MODE
MODE
MODE
MODE
MODE
MODE
Basic
Basic
(Interrupted by Precharge)
Random column Access
Sequential Counting
Interleave Counting
RAS Interrupt
CAS Interrupt
t
CCD
Burst Stop
Full Page
BRSW
= 1 CLK
1
2
4
8
At MRS A
BL=1, 2, 4, 8 and full page.
At MRS A
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
At MRS A
At auto precharge, t
At MRS A
At auto precharge, t
At MRS A
At MRS A
At MRS A
Wrap around mode(Infinite burst length) should be stopped by burst stop
Ras interrupt or CAS interrupt
At MRS A
Read burst =1, 2, 4, 8, full page write Burst =1
At auto precharge of write, t
Using burst stop command, any burst length control is possible.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
t
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
t
RDL
BDL
= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
3
3
2,1,0
2,1,0
2,1,0
2,1,0
2,1,0
9
= "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
= "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
= "1".
= "000".
= "001".
= "010".
= "011".
= "111".
- 24
RAS
RAS
should not be violated.
should not be violated.
RAS
should not be violated.
Rev. 1.2 April 2006
x32 SDRAM