ATF1508ASV-15AU100 Atmel, ATF1508ASV-15AU100 Datasheet - Page 12

• Manufacturer Part Number: ATF1508ASV-15AU100
• Description: IC CPLD 15NS LOW V 100TQFP
• Manufacturer: Atmel
• Series: ATF1508ASV(L)r

Specifications of ATF1508ASV-15AU100

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 128
• Number Of I /o: 80
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 80
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Details

AC Characteristics
12
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
t
t
t
t
t
t
t
t
t
t
t
t
PD1
PD2
SU
H
FSU
FH
COP
CH
CL
ASU
AH
ACOP
ACH
ACL
CNT
CNT
ACNT
ACNT
MAX
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ATF1508ASV(L)
Parameter
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
Global Clock Hold Time
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
Logic Control Delay
Internal Output Enable Delay
Output Buffer and Pad Delay
(Slow slew rate = OFF; V
Output Buffer and Pad Delay
(Slow slew rate = OFF; V
Output Buffer and Pad Delay
(Slow slew rate = ON; V
Output Buffer Enable Delay
(Slow slew rate = OFF; V
(1)
CCIO
CCIO
CCIO
CCIO
= 5V or 3.3V; C
= 5V; C
= 3.3V; C
= 5.0V; C
L
= 35 pF)
L
L
= 35 pF)
= 35 pF)
L
= 35 pF)
76.9
76.9
Min
100
1.0
11
3
3
0
3
5
5
5
4
6
6
-15
Max
3.5
15
12
15
13
13
9
2
2
2
8
1
6
3
3
3
5
7
13.5
58.8
83.3
Min
2.0
66
0
3
6
6
7
4
8
8
-20
Max
18.5
2.5
2.5
4.5
20
16
12
17
17
10
2
1
8
3
4
4
6
9
1408H–PLD–7/05
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns