ATF1508ASV-15AU100 Atmel, ATF1508ASV-15AU100 Datasheet - Page 14

• Manufacturer Part Number: ATF1508ASV-15AU100
• Description: IC CPLD 15NS LOW V 100TQFP
• Manufacturer: Atmel
• Series: ATF1508ASV(L)r

Specifications of ATF1508ASV-15AU100

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 128
• Number Of I /o: 80
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 80
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Details

Power-down Mode
Power Down AC Characteristics
Notes:
14
Symbol
t
t
t
t
t
t
t
t
t
t
IVDH
GVDH
CVDH
DHIX
DHGX
DHCX
DLIV
DLGV
DLCV
DLOV
1. For slow slew outputs, add t
2. Pin or product term.
ATF1508ASV(L)
Parameter
Valid I, I/O before PD High
Valid OE
Valid Clock
I, I/O Don’t Care after PD High
OE
Clock
PD Low to Valid I, I/O
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
(2)
Don’t Care after PD High
(2)
Don’t Care after PD High
(2)
(2)
before PD High
before PD High
Output AC Test Loads
The ATF1508ASV(L) includes two pins for optional pin-controlled power-down feature.
When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and
PD2 pin is high, the device supply current is reduced to less than 5 mA. During power-
down, all output data and internal logic states are latched and held. Therefore, all regis-
tered and combinatorial output data remain valid. Any outputs that were in a high-Z state
at the onset will remain at high-Z. During power-down, all input signals except the
power-down pin are blocked. Input and I/O hold latches remain active to ensure that
pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs using either power-down pin
may not use the PD pin logic array input. However, buried logic resources in this macro-
cell may still be used.
SSO
.
(1)(2)
703
8060
Min
15
15
15
-15
3.0V
Max
25
25
25
1
1
1
1
Min
20
20
20
-20
Max
30
30
30
1
1
1
1
1408H–PLD–7/05
Units
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs