ATF1508ASV-15AU100 Atmel, ATF1508ASV-15AU100 Datasheet - Page 8

• Manufacturer Part Number: ATF1508ASV-15AU100
• Description: IC CPLD 15NS LOW V 100TQFP
• Manufacturer: Atmel
• Series: ATF1508ASV(L)r

Specifications of ATF1508ASV-15AU100

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 128
• Number Of I /o: 80
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 80
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Details

Design Software
Support
Power-up Reset
Security Fuse Usage
8
ATF1508ASV(L)
All ATF1508 also have an optional power-down mode. In this mode, current drops to
below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
All power-down AC characteristic parameters are computed from external input or I/O
pins, with reduced-power bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, t
parameters, which include the data paths t
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
ATF1508ASV(L) designs are supported by several third-party tools. Automated fitters
allow logic synthesis using a variety of high-level description languages and formats.
The ATF1508ASV is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from V
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how V
system, the following conditions are required:
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving
3. The clock must remain stable during T
The ATF1508ASV has two options for the hysteresis about the reset level, V
and Large. To ensure a robust operating environment in applications where the device
is operated near 3.0V, Atmel recommends that during the fitting process users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on the command line after “file-
name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
4. If V
When the Large hysteresis option is active, I
amps as well.
A single fuse is provided to prevent unauthorized copying of the ATF1508ASV(L) fuse
patterns. Once programmed, fuse verify is inhibited. However, User Signature and
device ID remains accessible.
the clock pin high, and,
again.
CC
CC
falls below 2.0V, it must shut off completely before the device is turned on
rise must be monotonic,
D
LAD
.
, t
CC
CC
LAC
is reduced by several hundred micro-
crossing V
, t
IC
, t
ACL
RPA
, t
RST
ACH
, must be added to the AC
, all registers will be ini-
and t
CC
actually rises in the
SEXP
.
1408H–PLD–7/05
RST
, Small