XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 105

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

PLL Use Models
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Missing Input Clock or Feedback Clock
Clock Network Deskew
When the input clock or feedback clock is lost, the PLL will drive the output clocks to a
lower or higher frequency, causing all of the output clocks to increase/decrease in
frequency. The frequency increase/decrease can cause the clock output frequencies to
change to as much as six times the original configuration.
There are several methods to design with the PLL. The PLL wizard in ISE software can
assist with generating the various PLL parameters. Additionally, the PLL can be manually
instantiated as a component. It is also possible for the PLL to be merge with an IP core. The
IP core would contain and manage the PLL.
One of the predominant uses of the PLL is for clock network deskew.
PLL in this mode. The clock output from one of the O counters is used to drive logic within
the fabric and/or the I/Os. The feedback counter is used to control the exact phase
relationship between the input clock and the output clock (if, for example a 90° phase shift
is required). The associated clock waveforms are shown to the right for the case where the
input clock and output clock need to be phase aligned. This configuration is the most
flexible, but it does require two global clock networks
X-Ref Target - Figure 3-10
There are certain restrictions on implementing the feedback. The CLKFBOUT output can
be used to provide the feedback clock signal. The fundamental restriction is that both input
frequencies to the PFD must be identical. Therefore, the following relationship must be
met:
As an example, if ƒ
frequency are both 498 MHz. Since the M value in the feedback path is 3, both input
frequencies at the PFD are 166 MHz.
In another more complex scenario has an input frequency of 66.66 MHz and D = 2, M = 15,
and O = 2. The VCO frequency in this case is 500 MHz and the O output frequency is
250 MHz. Therefore, the feedback frequency at the PFD is 500/15 or 33.33 MHz, matching
the 66.66MHz/2 input clock frequency at the PFD.
1
IBUFG
2
3
CLKIN1
CLKFBIN
RST
PLL
IN
Figure 3-10: Clock Deskew Using Two BUFGs
is 166 MHz, D = 1, M = 3, and O = 1, then VCO and the clock output
CLKFBOUT
www.xilinx.com
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
f
------ -
D
IN
=
f
FB
4
6
=
BUFG
BUFG
f
------------ -
VCO
M
5
To Logic
(Figure
3-10).
1
2
3
4
5
6
Figure 3-10
PLL Use Models
Equation 3-8
UG190_3_10_040809
shows the
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