XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 162

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Chapter 4: Block RAM
Table 4-21: Block RAM ECC Port Names and Descriptions
162
Notes:
1. Hamming code implemented in the block RAM ECC logic detects one of three conditions: no detectable error, single-bit error
DI[63:0]
DIP[7:0]
WRADDR[8:0]
RDADDR[8:0]
WREN
RDEN
SSR
WRCLK
RDCLK
DO[63:0]
DOP[7:0]
SBITERR
DBITERR
ECCPARITY[7:0]
detected and corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and
DBITERR indicate these three conditions.
Port Name
(1)
(1)
Block RAM and FIFO ECC Port Descriptions
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Table 4-21
Data input bus.
Data input parity bus. Used in decode-only mode to input the precalculated ECC
parity bits.
Write address bus.
Read address bus.
Write enable. When WREN = 1, data will be written into memory. When WREN = 0,
write is disabled
Read enable. When RDEN = 1, data will be read from memory. When RDEN = 0, read
is disabled.
Not supported when using the block RAM ECC primitive. Always connect to GND.
Clock for write operations.
Clock for read operations.
Data output bus.
Data output parity bus. Used in encode-only mode to output the stored ECC parity
bits.
Single-bit error status.
Double-bit error status.
ECC encoder output bus.
lists and describes the block RAM ECC I/O port names.
www.xilinx.com
Signal Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010