XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 335

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The timing diagram in
I/O is an output switching to an input using 3-state control. The switching characteristics
shown in the diagram are specified in the Virtex-5 FPGA Data Sheet.
X-Ref Target - Figure 7-12
The activities of the OBUFT pin are controlled by the propagation and state of the
TSCONTROL signal from the ODDR flip-flop. The 3-state control data receipt on the
OBUF and IDDR flip-flop from a PAD are in parallel with each other, depending on the
IDELAY_VALUE setting the final value at the IDDR flip-flop input in response to a clock
edge is valid before or after the pad is driven from the 3-state control. After the 3-state
control propagates through to the PAD and the IODELAY has been switched to an input,
the IDDR setup time is the sole determiner of timing based on the IDELAY_VALUE and
other timing parameters defined in the Xilinx speed specification and represented in the
ISE tools.
Figure 7-12: Relevant Timing Signals to Examine IODELAY Timing when the IOB
TSCONTROL
ODDR CLK
IDDR CLK
PAD
Figure 7-12
ODDR CLK to 3-state
deassertion time.
Switches From an Output to an Input
www.xilinx.com
Previous PAD
Output Value
ODDR CLK to
shows the relevant signal timing for the case when the
IDELAY ready
T
OCKQ
T
IODDO_T
T
IOTP
Input/Output Delay Element (IODELAY)
T
IOPI
function of IDELAY_VALUE)
Pad to IDDR Setup Time is:
(where T
+ T
IODDO_IDATAIN
IODDO_IDATAIN
Input Value
New PAD
+ T
IODELAY_03_082107
is a
IDOCKD
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