EP1S20F672C6 Altera, EP1S20F672C6 Datasheet - Page 157

• Manufacturer Part Number: EP1S20F672C6
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672C6

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1853; EP1S20F672C6

Altera Corporation
July 2005
Notes to
(1)
(2)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 3–3. 32-Bit Stratix Device IDCODE
Device
The most significant bit (MSB) is on the left.
The IDCODE’s least significant bit (LSB) is always 1.
Tables 3–2
Version (4 Bits)
0000
0000
0000
0000
0000
0000
0000
and 3–3:
The Stratix device instruction register length is 10 bits and the USERCODE
register length is 32 bits.
register length and device IDCODE information for Stratix devices.
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 3–2. Stratix Boundary-Scan Register Length
Part Number (16 Bits)
0010 0000 0000 0001
0010 0000 0000 0010
0010 0000 0000 0011
0010 0000 0000 0100
0010 0000 0000 0101
0010 0000 0000 0110
0010 0000 0000 0111
Device
IDCODE (32 Bits)
Tables 3–2
Manufacturer Identity
(1)
and
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
Stratix Device Handbook, Volume 1
Boundary-Scan Register Length
3–3
(11 Bits)
show the boundary-scan
Configuration & Testing
1,317
1,797
2,157
2,253
2,529
3,129
3,777
LSB (1 Bit)
1
1
1
1
1
1
1
(2)
3–3