EP1S20F672C6 Altera, EP1S20F672C6 Datasheet - Page 49

• Manufacturer Part Number: EP1S20F672C6
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672C6

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1853; EP1S20F672C6

Altera Corporation
July 2005
The read and write operation of the memory is controlled by the WREN
signal, which sets the ports into either read or write modes. There is no
separate read enable (RE) signal.
Writing into RAM is controlled by both the WREN and byte enable
(byteena) signals for each port. The default value for the byteena
signal is high, in which case writing is controlled only by the WREN signal.
The byte enables are available for the ×18, ×36, and ×72 modes. In the
×144 simple dual-port mode, the two sets of byteena signals
(byteena_a and byteena_b) are combined to form the necessary
16 byte enables.
64K
32K
16K
8K
Table 2–9. M-RAM Block Configurations (True Dual-Port)
Table 2–10. Byte Enable for M-RAM Blocks
byteena[3..0]
×
×
×
×
72
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
9
18
36
Port A
Tables 2–10
datain ×18
[17..9]
64K × 9
[8..0]
–
–
–
–
–
–
v
v
v
v
and
2–11
32K × 18
summarize the byte selection.
Stratix Device Handbook, Volume 1
v
v
v
v
datain ×36
Notes
[26..18]
[35..27]
[17..9]
[8..0]
Port B
–
–
–
–
(1),
16K × 36
(2)
v
v
v
v
Stratix Architecture
datain ×72
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[17..9]
[8..0]
8K × 72
v
v
v
v
2–35