EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 438

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Stratix & Stratix GX I/O Standards
4–10
Stratix Device Handbook, Volume 2
Figure 4–7. SSTL-3 Class I Termination
Figure 4–8. SSTL-3 Class II Termination
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
– 0.3 V V
V
Figures 4–9
and output levels.
Figure 4–9. SSTL-2 Class I Termination
TT
to which the series and termination resistors are connected (see
I
Output Buffer
and 4–10). Stratix and Stratix GX devices support both input
Output Buffer
V
Output Buffer
CCIO
+ 0.3 V. SSTL-2 requires a 1.25-V V
25 Ω
25 Ω
25 Ω
V
TT
= 1.5 V
V
V
REF
REF
50 Ω
V
Z = 50 Ω
Z = 50 Ω
REF
= 1.25 V
Z = 50 Ω
= 1.5 V
= 1.5 V
V
V
TT
TT
V
TT
= 1.5 V
= 1.25 V
= 1.5 V
50 Ω
50 Ω
50 Ω
Input Buffer
Input Buffer
REF
Input Buffer
Altera Corporation
and a 1.25-V
June 2006