EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 706

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

PLLs & Clock Networks
10–22
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
(4)
(5)
Number of fast PLLs or True-
LVDS PLLs
Number of channels per
transmitter/receiver block
VCO frequency
Minimum input frequency
M = 4, 5, 6
Minimum input frequency
M = 7, 8, 9, 10
Table 10–8. Stratix & Stratix GX Fast PLL vs. APEX II & APEX 20K True-LVDS PLL
You can also use Stratix and Stratix GX device fast PLLs for general-purpose PLL applications.
EP20K400E and larger devices have two True-LVDS PLLs.
In APEX 20KE and APEX 20KC devices, M = 4, 7, or 8.
Stratix GX EP1SGX10 and EP1SGX25 contain two. EP1SGX10 contains four.
Stratix GX supports a frequency range of 300–1000 MHz (using DPA).
Table
Feature
(1)
10–8:
of the high-speed differential I/O data bus, do not have to be equal.
Additionally, Stratix and Stratix GX fast PLLs offer up to three clock
outputs, two multiplied high-speed PLL clocks to drive the
serializer/deserializer (SERDES) block and/or an external pin, and a
low-speed clock to drive the logic array. You can use fast PLLs for both
high-speed interfacing and for general-purpose PLL applications.
Table 10–8
PLLs and APEX II and APEX 20K True-LVDS PLLs.
The Stratix and Stratix GX fast PLL VCO frequency range is 300 to 840
MHz, and the APEX II True-LVDS PLL VCO frequency range is 200 MHz
to 1 GHz. Therefore, you must update designs that use a data rate of less
than 300 megabits per second (Mbps) to use the enhanced PLLs and M512
RAM blocks in SERDES bypass mode. Additionally, you must update
designs that use a data rate faster than 840 Mbps.
altpll Megafunction
Altera recommends that you replace instances of the altclklock
megafunction with the altpll megafunction to take advantage of new
Stratix and Stratix GX PLL features. Although in most cases you can
retarget your APEX II or APEX 20K design to a Stratix or Stratix GX
Four (EP1S25 and smaller
devices) fast PLLs
Eight (EP1S30 and larger
devices) fast PLLs
20
300 to 840 MHz
300 – M MHz
300 – M MHz
Stratix & Stratix GX
shows the differences between Stratix and Stratix GX fast
(5)
(4)
Four True-LVDS
PLLs
18
200 MHz to 1GHz
50 MHz
30 MHz
APEX II
Two True-LVDS
PLLs
18
200 to 840 MHz
50 MHz
M = 4
30 MHz
M = 7, 8
Altera Corporation
APEX 20KE
APEX 20KC
(2)
(3)
(3)
July 2005