EP20K400EFC672-1X Altera, EP20K400EFC672-1X Datasheet - Page 41

• Manufacturer Part Number: EP20K400EFC672-1X
• Description: IC APEX 20KE FPGA 400K 672-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K400EFC672-1X

• Number Of Logic Elements/cells: 16640
• Number Of Labs/clbs: 1664
• Total Ram Bits: 212992
• Number Of I /o: 488
• Number Of Gates: 1052000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1102

Figure 26. APEX 20KE Bidirectional I/O Registers
Notes to
(1)
(2)
Altera Corporation
Row, Column, FastRow,
or Local Interconnect
This programmable delay has four settings: off and three levels of delay.
The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Figure
26:
4 Dedicated
Inputs
Clock Inputs
4 Dedicated
4
Peripheral Control
Bus
12
VCC
OE[7..0]
CLK[1..0]
CLK[3..0]
ENA[5..0]
CLRn[1..0]
VCC
Input Pin to Input
Core to Output
Register Delay
Register Delay
VCC
VCC
VCC
VCC
VCC
APEX 20K Programmable Logic Device Family Data Sheet
Chip-Wide
Chip-Wide
Chip-Wide Reset
Core Delay (1)
Core Delay (1)
Input Pin to
Clock Enable
Input Pin to
Reset
Reset
Delay (1 )
Notes
Output Enable
Output Register
Chip-Wide
Input Register
OE Register
ENA
D
D
ENA
D
ENA
(1),
CLRN
CLRN
CLRN/
PRN
Q
Q
Q
(2)
Open-Drain
Slew-Rate
Output
Control
Core Delay (1)
Output Register
Input Pin to
t
CO
Delay
VCCIO
Optional
PCI Clamp
41