EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 20

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–20
Figure 1–5. Stratix IV GT Device Packaging Ordering Information
Document Revision History
Table 1–10. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 1
February 2011
March 2010
November 2009
F: FineLine BGA (FBGA)
H: Hybrid FineLine BGA
Package Type
Date
2 = 230k LEs
3 = 290k LEs
4 = 360k LEs
5 = 530k LEs
Family S i g n a t u r e
Aggregate Bandwidth
Device Density
Version
Figure 1–5
Table 1–10
3.0
3.2
3.1
EP4S
40G
100G
EP4S
■
■
■
■
■
■
■
■
■
■
■
■
■
40G
Updated
Applied new template.
Minor text edits.
Updated Table 1–1, Table 1–2, and Table 1–7.
Updated Figure 1–3.
Updated the “Stratix IV GT Devices” section.
Added two new references to the Introduction section.
Minor text edits.
Updated the “Stratix IV Device Family Overview”, “Feature Summary”, “Stratix IV GT
Devices”, “High-Speed Transceiver Features”, “FPGA Fabric and I/O Features”, “Highest
Aggregate Data Bandwidth”, “System Integration”, and “Integrated Software Platform”
sections.
Added Table 1–3, Table 1–6, and Table 1–9.
Updated Table 1–1, Table 1–2, Table 1–4, Table 1–5, Table 1–7, and Table 1–8.
Updated Figure 1–3, Figure 1–4, and Figure 1–5.
Minor text edits.
shows the ordering codes for Stratix IV GT devices.
lists the revision history for this chapter.
230
2
Table 1–7
F
Corresponds to pin count
40 = 1517 pins
45 = 1932 pins
Ball Array Dimension
40
and
Table
C
1–8.
2
Changes
ES
Chapter 1: Overview for the Stratix IV Device Family
ES: Engineering sample
Indicates specific device options
N: Lead-free devices
1, 2, 3 with 1 being the fastest
C: Commercial temperature (t
I :
Operating Temperature
Speed Grade
Optional Suffix
Industrial temperature (t
February 2011 Altera Corporation
Document Revision History
J
= 0°C to 100°C)
J
= 0 C to 85 C)