EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet

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... Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.3 Stratix IV Device Handbook Volume 1 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... LUT-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 ALM Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 LAB Power Management Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19 Chapter 3. TriMatrix Embedded Memory Blocks in Stratix IV Devices Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 April 2011 Altera Corporation Contents Stratix IV Device Handbook Volume 1 ...

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... Two-Multiplier Adder Sum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4– Complex Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24 Four-Multiplier Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26 High-Precision Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27 Multiply Accumulate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29 Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30 Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32 DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34 Stratix IV Device Handbook Volume 1 Contents April 2011 Altera Corporation ...

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... Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–42 PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–43 PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–44 Post-Scale Counters ( 5–46 Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–47 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–49 Bypassing a PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–50 Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–50 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–53 April 2011 Altera Corporation v Stratix IV Device Handbook Volume 1 ...

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... Termination Schemes for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38 Single-Ended I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38 Differential I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–41 LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–43 Differential LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–44 RSDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–45 Mini-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46 I/O Bank Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46 Stratix IV Device Handbook Volume 1 Contents April 2011 Altera Corporation ...

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... LVDS Interface with the Use External PLL Option Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–26 Left and Right PLLs (PLL_Lx and PLL_Rx 8–29 Stratix IV Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–30 Source-Synchronous Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31 Differential Data Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31 Differential I/O Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31 Transmitter Channel-to-Channel Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33 April 2011 Altera Corporation vii Stratix IV Device Handbook Volume 1 ...

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... PS Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–26 PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–31 PS Configuration Using a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–32 PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–32 JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–35 Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–40 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–40 Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–48 Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–50 Stratix IV Device Handbook Volume 1 Contents April 2011 Altera Corporation ...

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... Chapter 12. JTAG Boundary-Scan Testing in Stratix IV Devices BST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 BST Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 BSDL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 Chapter 13. Power Management in Stratix IV Devices Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1 April 2011 Altera Corporation ix Stratix IV Device Handbook Volume 1 ...

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... Stratix IV External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3 Temperature Sensing Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Stratix IV Device Handbook Volume 1 Contents April 2011 Altera Corporation ...

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... Chapter 10. Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices Revised: Part Number: SIV51010-3.3 Chapter 11. SEU Mitigation in Stratix IV Devices Revised: Part Number: SIV51011-3.2 Chapter 12. JTAG Boundary-Scan Testing in Stratix IV Devices April 2011 Altera Corporation February 2011 February 2011 February 2011 February 2011 February 2011 February 2011 ...

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... Revised: Part Number: SIV51012-3.2 Chapter 13. Power Management in Stratix IV Devices Revised: Part Number: SIV51013-3.2 Stratix IV Device Handbook Volume 1 February 2011 February 2011 Chapter Revision Dates April 2011 Altera Corporation ...

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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. April 2011 Altera Corporation Section I. Device Core ® IV Stratix IV Device Handbook Volume 1 ...

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... I–2 Stratix IV Device Handbook Volume 1 Section I: Device Core April 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Feature Summary PCI Express Compiler User Guide. February 2011 Altera Corporation ...

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... Figure 1–1 shows a high-level Stratix IV GX chip view. Figure 1–1. Stratix IV GX Chip View Note to Figure 1–1: (1) Resource counts vary with device selection, package selection, or both. February 2011 Altera Corporation chapter. (Note 1) General Purpose General Purpose PLL PLL I/O and Memory ...

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... General Purpose I/O and Memory Interface PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL PLL General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR PLL General Purpose I/O and Memory Interface February 2011 Altera Corporation ...

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... Figure 1–3 shows a high-level Stratix IV GT chip view. Figure 1–3. Stratix IV GT Chip View Note to Figure 1–3: (1) Resource counts vary with device selection, package selection, or both. February 2011 Altera Corporation chapter. (Note 1) General Purpose General Purpose PLL PLL I/O and Memory ...

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... Transaction layer support for up to two virtual channels (VCs) ■ Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features PCI Express Compiler User Guide. February 2011 Altera Corporation ...

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... On-package and on-chip power supply decoupling to satisfy transient current ■ requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors ■ Calibration circuitry for transmitter and receiver on-chip termination (OCT) resistors February 2011 Altera Corporation PCI Express Compiler User Guide. Stratix IV Device Handbook Volume 1 1–7 ...

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... (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in Stratix IV GX and Stratix IV GT devices (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in ■ Stratix IV E devices Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features February 2011 Altera Corporation ...

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... Programmable DQ group widths bits (includes parity bits) ■ Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate ■ register capabilities provide a robust external memory interface solution February 2011 Altera Corporation ) and on-chip parallel (R ) termination with auto-calibration for termination for differential I/Os D ratio of 8:1:1 to reduce loop inductance in the package— ...

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... I/O, power, and the JTAG pins to PCB, refer to the Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines Stratix IV GT Device Family Pin Connection Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Architecture Features and the Guidelines. February 2011 Altera Corporation ...

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Table 1–1 lists the Stratix IV GX device features. Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option ALMs 29,040 42,240 70,300 LEs 72,600 105,600 175,750 0.6 Gbps- 8.5 Gbps Transceivers — ...

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Table 1–1. Stratix IV GX Device Features (Part Feature EP4SGX70 EP4SGX110 EP4SGX180 Package Option M9K Blocks 462 660 (256 × 36 bits) M144K Blocks 16 16 (2048 × 72 bits) Total Memory (MLAB+M9K 7,370 9,564 13,627 +M144K) ...

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... Stratix IV devices accounts for the on-package F1517 F1760 F1932 (42.5 mm × 42.5 mm) (45 mm × 45 mm) (4), (6) (6) (6) — — — — — — KF40 — — KF40 — — KF40 KF43 NF45 KF40 KF43 NF45 KH40 (3) KF43 NF45 Package Information Datasheet for Altera Devices. ...

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... Altera Technical Support. ...

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... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (2) Four multiplier adder mode. (3) Total pairs of high-speed LVDS SERDES take the lowest channel count of R (4) This data is preliminary. February 2011 Altera Corporation EP4SE360 EP4SE530 780 1152 ...

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... The 1152-pin and 1517-pin for EP4SE530 and EP4SE820 devices are available only in the 42.5 mm × 42.5 mm Hybrid flip chip package. (4) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Information Datasheet for Altera Devices. ...

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... The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. (5) This data is preliminary. February 2011 Altera Corporation EP4S40G5 EP4S100G2 ...

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... Devices under the same arrow sign have vertical migration capability. (3) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information, refer to the Altera Device Package Information Data (4) EP4S40G5 and EP4S100G5 devices with 1517 pin-count are only available in 42.5-mm × 42.5-mm Hybrid flip chip packages. ...

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... Transceiver Count 180 D: 8 230 F: 16 290 H: 24 360 K: 36 530 N: 48 820 Package Type F: FineLine BGA (FBGA) H: Hybrid FineLine BGA February 2011 Altera Corporation Ball Array Dimension Corresponds to pin count 29 = 780 pins 35 = 1152 pins 40 = 1517 pins 43 = 1760 pins 45 = 1932 pins 1–19 ™ ...

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... Changes Table 1–7 and Table 1–8. Document Revision History Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices Speed Grade with 1 being the fastest Operating Temperature C: Commercial temperature ( Industrial temperature (t = 0°C to 100°C) J February 2011 Altera Corporation ...

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... Updated Table 1–2. ■ Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT ■ Device.” on page 1–15. July 2008 1.1 Revised “Introduction”. May 2008 1.0 Initial release. February 2011 Altera Corporation Changes Stratix IV Device Handbook Volume 1 1–21 ...

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... Stratix IV Device Handbook Volume 1 Chapter 1: Overview for the Stratix IV Device Family Document Revision History February 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... LAB Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows Logic Array Blocks ALMs Direct link interconnect from adjacent block Direct link interconnect to adjacent block Column Interconnects of Variable Speed & Length Figure 2–2. February 2011 Altera Corporation ...

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... Simple dual-port SRAM LUT-based- Simple dual-port SRAM LUT-based- Simple dual-port SRAM Note to Figure 2–2: (1) You can use the MLAB ALM as a regular LAB ALM or configure dual-port SRAM, as shown. February 2011 Altera Corporation TriMatrix Embedded Memory Blocks in Stratix IV (1) ALM (1) ALM (1) ALM (1) ...

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... Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Local Interconnect LAB Logic Array Blocks Direct-link interconnect from the right LAB, TriMatrix memory block, DSP block, or IOE output ALMs Direct-link interconnect to right February 2011 Altera Corporation ...

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... ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function with up to six inputs and certain seven-input functions. February 2011 Altera Corporation There are two unique clock signals per LAB. labclk0 ...

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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Figure 2–5 shows a high-level block diagram of carry_in reg_chain_in labclk adder0 D reg0 adder1 D reg1 reg_chain_out carry_out Adaptive Logic Modules To general or local routing To general or Q local routing To general or Q local routing To general or local routing February 2011 Altera Corporation ...

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... For each set of output drivers, two ALM outputs can drive column, row, or direct-link routing connections. One of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. February 2011 Altera Corporation syncload aclr[1:0] carry_in ...

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... Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices 2–4. Adaptive Logic Modules “LAB Control February 2011 Altera Corporation ...

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... Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, and 5 and 2. Normal mode provides complete backward-compatibility with four-input LUT architectures. February 2011 Altera Corporation dataf0 datae0 combout0 ...

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... Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices (Note 1) 6-Input LUT D Q reg0 D Q reg1 labclk Adaptive Logic Modules Figure 2–8). If you use To general or local routing To general or local routing To general or local routing February 2011 Altera Corporation ...

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... Note to Figure 2–9: (1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. February 2011 Altera Corporation shows the template of supported seven-input functions using Figure 2–9 LUT combout0 D reg0 LUT 2– ...

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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices carry_in adder0 4-Input LUT D Q reg0 4-Input LUT adder1 4-Input LUT D Q 4-Input reg1 LUT carry_out Adaptive Logic Modules Figure 2–10, the carry-in To general or local routing To general or local routing To general or local routing To general or local routing February 2011 Altera Corporation ...

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... ALMs in the next LAB within the column. In every alternate LAB column, the top half can be bypassed; in the other MLAB columns, the bottom half can be bypassed. For more information about carry-chain interconnects, refer to on page 2–18. February 2011 Altera Corporation 2–13 “ALM Interconnects” Stratix IV Device Handbook Volume 1 ...

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... ALM using this feature. shared_arith_in carry_in labclk 4-Input LUT D Q reg0 4-Input LUT 4-Input LUT D Q 4-Input reg1 LUT carry_out shared_arith_out Adaptive Logic Modules To general or local routing To general or local routing To general or local routing To general or local routing February 2011 Altera Corporation ...

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... LUT register shares its clock, clock enable, and asynchronous clear sources with the top dedicated register. combinational blocks within the ALM. Figure 2–12. LUT Register from Two Combinational Blocks clk aclr datain(datac) sclr February 2011 Altera Corporation 2–18. Figure 2–12 shows the register constructed using two 4-input LUT 5-input LUT 2– ...

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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices reg_chain_in datain aclr aclr datain sclr regout latchout sdata regout aclr datain sdata regout reg_chain_out Adaptive Logic Modules lelocal 0 leout 0 a leout 0 b lelocal 1 leout 1 a leout 1 b February 2011 Altera Corporation ...

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... Figure 2–14: (1) You can use the combinational or adder logic to implement an unrelated, un-registered function. For more information about the register chain interconnect, refer to Interconnects” on page February 2011 Altera Corporation Figure 2–14). The Quartus II Compiler automatically takes (Note 1) From previous ALM within the LAB ...

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... Local interconnect routing among ALMs in the LAB ALM 1 Carry chain & shared arithmetic chain routing to adjacent ALM ALM 2 Local ALM 3 interconnect ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 ALM 9 ALM 10 Adaptive Logic Modules Register chain routing to adjacent ALM's register input February 2011 Altera Corporation ...

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... Removed “Referenced Documents” section. Updated Figure 2–6. ■ November 2008 2.0 Made minor editorial changes. ■ May 2008 1.0 Initial release. February 2011 Altera Corporation Power Optimization chapter in volume 2 of the Quartus II Changes Figure 2–6. 2–19 Stratix IV Device Handbook Volume 1 ...

Page 56

... Stratix IV Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices Document Revision History February 2011 Altera Corporation ...

Page 57

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 58

... Outputs set to old data or don’t care Built-in support in ×64-wide SDP mode or soft IP support using the Quartus II software Total RAM Bits (Including MLABs) (Kb) (Kb) 14,283 17,133 18,144 22,564 20,736 27,376 23,130 33,294 6,462 7,370 8,244 9,564 February 2011 Altera Corporation ...

Page 59

... LSB of the data bus. For example, if you use a RAM block in ×18 mode, with byteena = 01, data[8..0] is enabled, and data[17..9] id disabled. Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled. Byte enables are active high. February 2011 Altera Corporation Total Dedicated RAM Bits M144K (Dedicated Memory Blocks Only) ...

Page 60

... RAM must not exceed half of the target block size. Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices ABCD 01 11 ABFF FFFF ABXX XXCD ABCD ABFF FFCD ABCD Overview a1 a2 XXXX XX FFCD ABCD ABFF FFCD ABCD ABFF FFCD ABCD February 2011 Altera Corporation ...

Page 61

... Figure 3–2. Address Clock Enable Figure 3–3 shows the address clock enable waveform during the read cycle. Figure 3–3. Address Clock Enable During Read Cycle Waveform inclock rdaddress addressstall latched address (inside memory) q (synch) q (asynch) February 2011 Altera Corporation 1 address[0] address[0] 0 register 1 address[N] register address[N] 0 ...

Page 62

... You can selectively enable asynchronous clears per logical memory using the Quartus II RAM MegaWizard Plug-In Manager. f For more information, refer to the Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices data wren Internal Memory (RAM and ROM) User Overview “Memory Modes” Figure 3–5 Guide. February 2011 Altera Corporation ...

Page 63

... Table 3–3. Truth Table for ECC Status Flags Status No error Single error and fixed Double error and no fix Illegal Illegal Illegal Illegal 1 You cannot use the byte enable feature when ECC is engaged. 1 Read-during-write “old data mode” is not supported when ECC is engaged. February 2011 Altera Corporation eccstatus[2] eccstatus[ ...

Page 64

... This applies to both read and write operations. Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices RAM Array 64 Memory Modes 8 SECDED Comparator Encoder Flag Error Generator Locator 64 3 Status Flags Error Correction Block 64 Data Output February 2011 Altera Corporation ...

Page 65

... TriMatrix memory blocks in single-port mode. Table 3–4. Port Width Configurations for MLABs, M9K, and M144K Blocks (Single-Port Mode) Port Width Configurations February 2011 Altera Corporation Figure 3–7 shows the single-port RAM (Note 1) data[ ] address[ ] ...

Page 66

... M9K blocks in simple Write Port 2K × × 8 512 × 16 256 × Memory Modes A1 11 EEEE FFFF A1(old data) DDDD EEEE rden q[ ] rdclock 1K × 9 512 × 18 256 × 36 — — — — — — — — — February 2011 Altera Corporation ...

Page 67

... MLABs only support a write-enable signal. For MLABs, you can set the same-port read-during-write behavior to don’t care and the mixed-port read-during-write behavior to either don’t care or old data. The available choices depend on the configuration of the MLAB. There is no “new data” option for MLABs. February 2011 Altera Corporation Write Port 2K × × 8 512 × ...

Page 68

... Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices dout0 doutn dout0 doutn Memory Modes din4 din5 din6 din4 din5 din6 b2 b3 February 2011 Altera Corporation ...

Page 69

... Table 3–7. M9K Block Mixed-Width Configuration (True Dual-Port Mode) Read Port 8K × × × × 8 512 × × 9 512 × 18 February 2011 Altera Corporation (Note 1) data_a[ ] data_b[ ] address_a[ ] address_b[] wren_a wren_b byteena_a[] byteena_b[] addressstall_a ...

Page 70

... Memory Modes Write Port 16K × × × 36 — — — — — — — — — din4 din5 din6 dout3 din5 din4 b2 b3 dout2 dout1 February 2011 Altera Corporation ...

Page 71

... Figure 3–14 shows the TriMatrix memory block in shift-register mode. Figure 3–14. Shift-Register Memory Configuration Shift Register m-Bit Shift Register W m-Bit Shift Register W m-Bit Shift Register W m-Bit Shift Register W February 2011 Altera Corporation 3– Number of Taps W W Stratix IV Device Handbook Volume 1 ...

Page 72

... Independent v Input/output Read/write — v Single clock Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Guide. Simple Single-Port Mode Dual-Port Mode — — — Clocking Modes SCFIFO and ROM Mode FIFO Mode v — v — v — February 2011 Altera Corporation ...

Page 73

... For example, the Quartus II software may spread memory out across multiple memory blocks when resources are available to increase the performance of the design. You can manually assign memory to a specific block size using the RAM MegaWizard Plug-In Manager. February 2011 Altera Corporation 3–17 Stratix IV Device Handbook Volume 1 ...

Page 74

... Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices chapter. Figure 3–15 shows the difference between the Port A data in Port A data out Design Considerations Logic Array Blocks and Port B data in Mixed-port data flow Same-port data flow Port B data out February 2011 Altera Corporation ...

Page 75

... M9K and M144K blocks. Figure 3–17. M9K and M144K Blocks Same-Port Read-During-Write: New Data Mode clk_a address rdena wrena bytenna data_a q_a (asyn) February 2011 Altera Corporation FFFF XX FFFF A1(old data) A0(old data) XX ...

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... A0 (old data) B423 A1(old data) old old Internal Memory (RAM and ROM) User A0 A0 AAAA BBBB CCCC DDDD AAAA AABB A0 (old data) Design Considerations A1 11 EEEE FFFF DDDD EEEE A1 A1 EEEE FFFF 10 01 A1(old data) DDDD DDEE February 2011 Altera Corporation ...

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... M9K and M144K blocks. Figure 3–21. M9K and M144K Blocks Mixed-Port Read-During Write: Old Data Mode clk_a&b wrena address_a data_a bytenna rdenb address_b q_b_(asyn) February 2011 Altera Corporation A0 A0 AAAA BBBB CCCC DDDD ...

Page 78

... For more information about .mif files, refer to the User Guide and the Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices A0 AAAA BBBB CCCC DDDD XXXX (unknown data) Internal Memory (RAM and ROM) Quartus II Handbook. Design Considerations A1 EEEE FFFF 11 A1 February 2011 Altera Corporation ...

Page 79

... Removed “Referenced Documents” section. ■ November 2008 2.0 Updated “Power-Up Conditions and Memory Initialization” on page 3–20 May 2008 1.0 Initial release. February 2011 Altera Corporation Changes “Byte Enable Support” and “Power-Up Conditions and Memory Initialization” 3–23 Stratix IV Device Handbook Volume 1 ...

Page 80

... Stratix IV Device Handbook Volume 1 Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices Document Revision History February 2011 Altera Corporation ...

Page 81

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 82

... February 2011 Altera Corporation Four Multiplier Adder Mode 18 × 18 Multipliers 1288 1040 1024 960 384 512 920 1288 832 1,040 1,024 1,024 ...

Page 83

... Figure 4–1. Overview of DSP Block Signals 34 Control 144 288 Input Data 144 February 2011 Altera Corporation Independent Input and Output Multiplication Operators 9 × × × 18 Multipliers Multipliers Multipliers Complex 1,288 ...

Page 84

... Therefore, there are eight 18 × 18 multiplier functionalities per DSP block. Stratix IV Device Handbook Volume 1 and Figure 4–2. P[36.. [17..0] × B [17..0] ± Figure 4–2 is useful for building more complex structures, Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Simplified DSP Operation [17..0] × B [17.. +/- P[36..0] February 2011 Altera Corporation ...

Page 85

... Depending on the mode you select, you can bypass all register stages except accumulation and loopback mode. In these two modes, one set of registers must be enabled. If the register set is not enabled, an infinite loop occurs. Figure 4–3. Four-Multiplier Adder and Accumulation Capability 144 Input Data Half-DSP Block February 2011 Altera Corporation Z[37.. [36.. [43.. [43..0] ± n-1 provides a sum of four 18 × ...

Page 86

... Stratix IV Device Handbook Volume 1 Figure 4–4. Detailed examples are described in From Previous Half DSP Block 44 To Next Half DSP Block Figure 4–4 is the optional rounding and saturation unit (RSU). This Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Simplified DSP Operation 44 Result[] 44 February 2011 Altera Corporation ...

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... Figure 4–6 on page 4–9 Figure 4–5. Stratix IV Full DSP Block 144 Input Data 144 Input Data February 2011 Altera Corporation shows a more detailed top-level view of the DSP block. From Previous Half DSP Block 44 Top Half DSP Block 44 Bottom Half DSP Block To Next Half DSP Block 4– ...

Page 88

... Chainout 1st Stage Stage Adder Add/Sub Add/Acc No No — — — — Yes No — — — — — — Both — Yes Yes Both Add Only Yes Yes Both Both No — — — — Add Only February 2011 Altera Corporation ...

Page 89

... Block output for accumulator overflow and saturate overflow. (2) Block output for saturation overflow of chainout. (3) The chainin port must only be connected to chainout of the previous DSP blocks and must not be connected to general routings. February 2011 Altera Corporation shows a list of DSP block dynamic signals. signa ...

Page 90

... DSP block. Use the ninth register bank to balance the latency requirements when using the chained cascade feature. Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions February 2011 Altera Corporation ...

Page 91

... DSP blocks. The dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular FPGA routing resources. February 2011 Altera Corporation Figure 4–7. ...

Page 92

... Signed (logic 1) Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions Figure 4–6 on page 4–9. In 4–22. 36 × 36 Double v v — — — — 4–24. Table 4–4 lists the sign of the Result Unsigned Signed Signed Signed February 2011 Altera Corporation ...

Page 93

... You cannot use the second-stage adder independently from the multiplier and first-stage adder. February 2011 Altera Corporation 4–22. shows that the outputs of the multipliers are the only outputs shows that the output from the first-stage adder can either 4– ...

Page 94

... For more information, refer to “Stratix IV Operational Mode Descriptions” on page Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV DSP Block Resource Descriptions “Stratix IV Operational Mode Descriptions” on 4–15. February 2011 Altera Corporation ...

Page 95

... For operand widths from bits × 12 multiplier is implemented, and for operand widths from bits × 18 multiplier is implemented. This is done by the Quartus II software by zero-padding the LSBs. the independent multiplier operation. signals for the DSP block. February 2011 Altera Corporation Figure 4–8, Figure 4–9, and Figure 4–10 Table 4– ...

Page 96

... Note to Figure 4–8: (1) Block output for accumulator overflow and saturate overflow. Stratix IV Device Handbook Volume 1 signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate Half-DSP Block Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions overflow (1) 36 result_0 result_1[ ] February 2011 Altera Corporation ...

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... Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–9. 12-Bit Independent Multiplier Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[11..0] datab_0[11..0] dataa_1[11..0] datab_1[11..0] dataa_2[11..0] datab_2[11..0] February 2011 Altera Corporation signa signb Half-DSP Block 4–17 24 result_0 result_1 result_2[ ] ...

Page 98

... DSP block to pipeline the multiplier result, increasing the performance of the DSP block. 1 The rounding and saturation logic unit is supported for 18-bit independent multiplier mode only. Stratix IV Device Handbook Volume 1 signa signb Half-DSP Block Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions 18 result_0 result_1 result_2 result_3[ ] February 2011 Altera Corporation ...

Page 99

... Figure 4–11. 36-Bit Independent Multiplier Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] February 2011 Altera Corporation signa signb + + Half-DSP Block 4–19 Figure 4–11 result[ ] Stratix IV Device Handbook Volume 1 ...

Page 100

... Figure 4–12. Double Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Stratix IV Device Handbook Volume 1 Figure 4–12 and Figure signa signb + + Half-DSP Block Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions 4–13 result[ ] February 2011 Altera Corporation ...

Page 101

... February 2011 Altera Corporation clock[3..0] signa ena[3..0] signb aclr[3..0] Two Multiplier "0" Adder Mode "0" + Double Mode Mode Unsigned Multiplier 36 55 108 result[ ] ...

Page 102

... DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions shows the DSP block configured in the loopback mode. This Figure 4–14 on February 2011 Altera Corporation ...

Page 103

... Figure 4–14. Two-Multiplier Adder Mode Shown for a Half DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[17..0] datab_0[17..0] dataa_1[17..0] datab_1[17..0] Note to Figure 4–14: (1) Block output for accumulator overflow and saturate overflow. February 2011 Altera Corporation signa signb output_round output_saturate + Half-DSP Block 4–23 overflow (1) result[ ] Stratix IV Device Handbook Volume 1 ...

Page 104

... Equation 4–4 Equation 4–4. Complex Multiplication Equation Stratix IV Device Handbook Volume 1 signa signb output_round output_saturate + shows a complex multiplication jb) × jd) = ((a × c) – (b × d)) + j((a × × c)) Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions overflow (1) result[ ] February 2011 Altera Corporation ...

Page 105

... This mode automatically assumes all inputs are using signed numbers. Figure 4–16. Complex Multiplier Using Two-Multiplier Adder Mode clock[3..0] ena[3..0] aclr[3.. February 2011 Altera Corporation Figure 4–16 shows an 18-bit complex signa signb Half-DSP Block 4– ...

Page 106

... Block output for accumulator overflow and saturate overflow. Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure and Equation 4–3 on page 4–5. signa signb output_round output_saturate + + + 4–17, the DSP block can overflow (1) result[ ] February 2011 Altera Corporation ...

Page 107

... The results of these two adder blocks are then summed in the second stage adder block to produce the final result: Z[54.. [53.. where A[17..0] × B[35.. C[17..0] × D[35..0] 1 February 2011 Altera Corporation [53..0] 1 4–27 Figure 4–18 on Stratix IV Device Handbook Volume 1 ...

Page 108

... Half-DSP Block Note to Figure 4–18: (1) Block output for accumulator overflow and saturate overflow. Stratix IV Device Handbook Volume 1 signa signb + P 0 << <<18 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions overflow (1) result[ ] February 2011 Altera Corporation ...

Page 109

... Half-DSP Block Note to Figure 4–19: (1) Block output for saturation overflow of chainout. A single DSP block can implement up to two independent 44-bit accumulators. February 2011 Altera Corporation Equation 4–3 on page 4–5. Figure 4–19 signa signb output_round output_saturate + + + 4– ...

Page 110

... Two control signals, rotate and shift_right, together with the signa and signb signals, determine the shifting operation. shift operations. Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions Figure 4–20 on Table 4–5 on page 4–31 lists examples of February 2011 Altera Corporation ...

Page 111

... Unsigned Unsigned LSL[N] Logical Shift Right Unsigned Unsigned LSR[32-N] Arithmetic Shift Left Signed Unsigned ASL[N] Arithmetic Shift Right Signed Unsigned ASR[32-N] Rotation ROT[N] Unsigned Unsigned February 2011 Altera Corporation signa signb rotate shift_right + + + Signb Shift Rotate A-input 0 0 0xAABBCCDD 1 0 0xAABBCCDD ...

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... Stratix IV Operational Mode Descriptions Add to Integer Result 1 0110 0 0011 0 0010 1 0100 1 1110 0 1011 1 1110 0 1100 Round-To-Nearest-Even ➱ 010111 0110 ➱ 001101 0011 001010 ➱ 0010 001110 ➱ 0100 ➱ 110111 1110 ➱ 101101 1011 ➱ 110110 1110 ➱ 110010 1100 February 2011 Altera Corporation ...

Page 113

... Figure 4–21. Rounding and Saturation Locations 16 User defined SAT Positions (bit 43-28 For symmetric saturation, the RND bit position is also used to determine where the LSP for the saturated data is located. February 2011 Altera Corporation (n–1) (n– For example, for 32 bits: Symmetric SAT Result 7FFFFFFFFh 800000001h 4–21. 29 ...

Page 114

... B)], when used for an accumulation type of operation × B)], when used for an accumulation type of operation × B)]] Table 4–9 lists the dynamic signals for the DSP block. Function Chapter 4: DSP Blocks in Stratix IV Devices Stratix IV Operational Mode Descriptions 4–8. However, for Count February 2011 Altera Corporation ...

Page 115

... DSP block-wide asynchronous clear signals (active low). aclr2 aclr3 Total Count per Full Block Software Support Altera provides two distinct methods for implementing various modes of the DSP block in a design—instantiation and inference. Both methods use the following Quartus II megafunctions: ■ lpm_mult ■ ...

Page 116

... November 2008 2.0 Updated Figure 4–16. ■ Updated Figure 4–18. ■ May 2008 1.0 Initial release. Stratix IV Device Handbook Volume 1 Chapter 4: DSP Blocks in Stratix IV Devices Document Revision History “Synthesis” section in volume 1 of the Quartus II Changes February 2011 Altera Corporation ...

Page 117

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 118

... Stratix IV GX and Stratix IV E Device Family Pin Connection Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Source of Clock Resource 16 GCLKs + 64 RCLKs (4) 16 GCLKs + 88 RCLKs Figure 5–1 through Figure 5–4 on page Clock Networks in Stratix IV Devices 5–5. Guidelines. February 2011 Altera Corporation ...

Page 119

... Figure 5–1 shows the CLK pins and PLLs that can drive the GCLK networks in Stratix IV devices. Figure 5–1. GCLK Networks L1 L2 CLK[0.. February 2011 Altera Corporation CLK[12..15 GCLK[12..15] GCLK[0..3] GCLK[8..11] GCLK[4.. CLK[4..7] 5–3 ...

Page 120

... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–4 on page 5–5 show the CLK pins and PLLs that can CLK[12..15] T1 RCLK[54..63] RCLK[44..53] RCLK[38..43] RCLK[0.. RCLK[6..11] RCLK[32..37] RCLK[12..21] RCLK[22..31] B1 CLK[4..7] Clock Networks in Stratix IV Devices (Note 1) R2 CLK[8..11] February 2011 Altera Corporation ...

Page 121

... A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and another four core signals can drive into RCLK[54..63] at any one time. February 2011 Altera Corporation CLK[12..15] ...

Page 122

... Figure 5–5. PCLK Networks (EP4SGX70 and EP4SGX110 Devices) L2 CLK[0..3] Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–5 through Figure 5–8 on page 5–8 CLK[12..15] T1 PCLK[0..13] PCLK[42..56 PCLK[14..27] PCLK[28..41] B1 CLK[4..7] Clock Networks in Stratix IV Devices are collections of R2 CLK[8..11] February 2011 Altera Corporation ...

Page 123

... Figure 5–7. PCLK Networks (EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE530, and EP4SGX530 Devices) (Note CLK[0.. Note to Figure 5–7: (1) The EP4S40G5 device has eight PLLs. For more information about PLL availability, refer to February 2011 Altera Corporation CLK[12..15 PCLK[0..10] PCLK[77..87] PCLK[11..21] PCLK[66..76 PCLK[22..32] PCLK[55..65] PCLK[33 ...

Page 124

... Figure 5–8. PCLK Networks (EP4SE820 Device CLK[0.. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices CLK[12..15 PCLK[0..15] PCLK[116..131] PCLK[16..32] PCLK[99..115 PCLK[33..49] PCLK[82..98] PCLK[50..65] PCLK[66..81 CLK[4..7] Clock Networks in Stratix IV Devices R1 R2 CLK[8..11 February 2011 Altera Corporation ...

Page 125

... This is a good option for routing global reset and clear signals or routing clocks throughout the device. February 2011 Altera Corporation Figure 5–9 16 GCLK ...

Page 126

... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Networks in Stratix IV Devices Figure 5–10 shows the dual-regional clock region. Clock pins or PLL outputs can drive half of the device to create side-wide clocking regions for improved interface timing. Table 5–2 and Table 5–3 on page February 2011 Altera Corporation 5–11. ...

Page 127

... RCLK [13, 17, 21, 23, — — 27, 31] RCLK [12, 16, 20, 22, — — 26, 30] — — RCLK [15, 19, 25, 29] — — RCLK [14, 18, 24, 28] — — RCLK [35, 41] February 2011 Altera Corporation and Table 5–6 on page 5–13. CLK (p/n Pins — — — — — ...

Page 128

... Pin-Out Files for February 2011 Altera Corporation ...

Page 129

... Only PLL counter outputs can drive the GCLK networks. Table 5–6 lists how the PLL clock outputs connect to the RCLK networks. Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs Clock Resource RCLK[0..11] RCLK[12..31] RCLK[32..43] RCLK[44..63] February 2011 Altera Corporation PLL Number ...

Page 130

... GCLK Clock Networks in Stratix IV Devices (Note 1) (Part — — — — — — v — — — — — v — — — — — — — — — — — Pin Internal Logic Static Clock Select (2) Internal Logic February 2011 Altera Corporation ...

Page 131

... Quartus II software. The dynamic clock enable or disable feature allows the internal logic to control power-up or power-down synchronously on the GCLK and RCLK networks, including dual-regional clock regions. This function is independent of the PLL and is applied directly on the clock network, as shown in Figure 5–12. February 2011 Altera Corporation CLKp CLKn (2) Pin Pin ...

Page 132

... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–13 shows the external PLL output Clock Control Block (ALTCLKCTRL) Megafunction PLL Counter Outputs Static Clock Select (1) Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) PLL_<#>_CLKOUT pin Clock Networks in Stratix IV Devices February 2011 Altera Corporation ...

Page 133

... AND gate with R2 bypassed output of AND gate with R2 not bypassed Note to Figure 5–15: (1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the PLL_<#>_CLKOUT pins. February 2011 Altera Corporation (1) (1) ( Figure 5–15 shows a waveform example for 5– ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure (1) 4 clk[n+3..n] (2) Adjacent PLL output (1) 4 PLL_<L1/L4/R1/R4>_CLK (1) GCLK/RCLK (2) 4 CLK[0..3] or CLK[8..11] (3) 4 Clock Networks in Stratix IV Devices 5–16; the corresponding clock Figure 5–17. inclk0 To the clock switchover block inclk1 inclk0 inclk1 February 2011 Altera Corporation ...

Page 135

... H1517 — v EP4S100G2 F1517 — EP4S100G3 F1932 v v EP4S100G4 F1932 v H1517 — EP4S100G5 v v F1932 v EP4SE230 F780 — v H780 — EP4SE360 v F1152 — v H1152 — EP4SE530 H1517 v v F1760 February 2011 Altera Corporation Transceiver Clocking in Stratix IV Devices — — — — ...

Page 136

... Stratix IV Left/Right PLLs 512 2 single-ended or 1 differential pair 4 single-ended or 4 differential pin pairs Single-ended only Yes (3) February 2011 Altera Corporation ...

Page 137

... Figure 5–18. PLL Locations in Stratix IV Devices L1 PLL_L1_CLK Left/Right PLLs L2 CLK[0..3] L3 Left/Right PLLs L4 PLL_L4_CLK February 2011 Altera Corporation (Note 1) Stratix IV Top/Bottom PLLs Through GCLK and RCLK and a dedicated path between adjacent PLLs All except LVDS clock network compensation No No Down to 96.125 ps ...

Page 138

... Chapter 5: Clock Networks and PLLs in Stratix IV Devices ) is equal to (m) times the input reference clock (f VCO ) to the PFD is equal to the input clock ( that is applied to the other input of the PFD. REF PLLs in Stratix IV Devices ). The input divided by the IN ) applied to one input of the FB February 2011 Altera Corporation ...

Page 139

... Each top and bottom PLL supports six clock I/O pins, organized as three pairs of pins: 1st pair—two single-ended I/O or one differential I/O ■ ■ 2nd pair—two single-ended I/O or one differential external feedback input (FBp/FBn) ■ 3rd pair—two single-ended I/O or one differential input February 2011 Altera Corporation Lock locked Circuit 8 ÷2 ÷ ...

Page 140

... These external clock enable signals are available only when using the ALTCLKCTRL megafunction. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices clkena4 (3) clkena2 (3) clkena3 (3) clkena5 (3) PLL_<#>_CLKOUT3 PLL_<#>_FBp/CLKOUT1 (1), (2) PLL_<#>_FBn/CLKOUT2 (1), (2) PLLs in Stratix IV Devices Internal Logic (1), (2) PLL_<#>_CLKOUT4 (1), (2) February 2011 Altera Corporation ...

Page 141

... Stratix IV PLLs can also drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not need external PLL clocking. February 2011 Altera Corporation and Figure 5–21. Therefore, one counter or frequency can drive ...

Page 142

... Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL. Stratix IV Device Handbook Volume 1 ...

Page 143

... PLL. If the PLL input is instead fed by a non-dedicated input (using the GCLK network), the output clock may not be perfectly aligned with the input clock. February 2011 Altera Corporation Top and Bottom PLLs Yes ...

Page 144

... IOE input register. Figure 5–22 shows an example waveform of the clock and data in this mode. Altera recommends source synchronous mode for source-synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Figure 5– ...

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... Figure 5–24. Phase Relationship Between the PLL Clocks in No Compensation Mode External PLL Clock Outputs (1) Note to Figure 5–24: (1) The PLL clock outputs lag the PLL input clocks depending on routine delays. February 2011 Altera Corporation Data pin PLL reference clock at input pin Data at register ...

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... Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–25 shows an example waveform of the PLL clocks’ phase Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port PLLs in Stratix IV Devices Figure 5–26 shows ZDB mode February 2011 Altera Corporation ...

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... When using external feedback mode, you must use the same I/O standard on the input clock, feedback input, and output clocks. Left and right PLLs support this mode when using single-ended I/O standards only. February 2011 Altera Corporation ÷C0 PFD CP/LF VCO ÷ ...

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... Clock Port (1) Dedicated PLL Clock Outputs (1) fbin Clock Input Pin ÷C0 PFD CP/LF VCO ÷C1 ÷m (M/N). Each output port has a unique post-scale counter that in PLLs in Stratix IV Devices PLL_<#>_CLKOUT# PLL_<#>_CLKOUT# fbout external board fbin trace February 2011 Altera Corporation ...

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... VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings. For example and C1 = 20, the cascaded value is C0 × 800. 1 Post-scale counter cascading is set in the configuration file. You cannot set this using PLL reconfiguration. February 2011 Altera Corporation VCO Output C0 C1 VCO Output C2 ...

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... Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices 1 1 Φ fine 8 VCO 8f 8Mf VCO is 100 MHz and then f REF PLLs in Stratix IV Devices Equation 5–1 N REF Φ is 800 MHz and VCO fine February 2011 Altera Corporation ...

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... Stratix IV devices support dynamic phase-shifting of VCO phase taps only. You can reconfigure the phase shift any number of times. Each phase shift takes about one SCANCLK cycle, allowing you to implement large phase shifts quickly. February 2011 Altera Corporation shows the coarse-resolution phase shifts are implemented by delaying C − 1 Φ ...

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... Gain Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–32 shows, these points correspond to approximately the same Frequency Frequency PLLs in Stratix IV Devices Increasing the PLL's bandwidth in effect pushes the open loop response out. February 2011 Altera Corporation ...

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... Quartus II software. The components are the loop filter resistor, R, the high frequency capacitor and the charge pump current Figure 5–33. Loop Filter Programmable Components February 2011 Altera Corporation PFD ...

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... When the clkswitch signal goes high, it overrides the automatic clock switchover function. As long as the clkswitch signal is high, further switchover action is blocked. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices February 2011 Altera Corporation ...

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... PLL may lose lock after the switchover is completed and needs time to re-lock. 1 Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover. February 2011 Altera Corporation ...

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... MHz. The ALTPLL MegaWizard Plug-in Manager notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices inclk0 inclk1 (1) muxout clkbad0 clkbad1 activeclock PLLs in Stratix IV Devices February 2011 Altera Corporation ...

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... When the clkswitch signal goes high again, the process repeats. clkswitch and automatic switch only work if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available. February 2011 Altera Corporation inclk0 inclk1 muxout ...

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... PLL. However, be aware that the low-bandwidth PLL also increases lock time. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Clock Switch Control Logic n Counter muxout refclk Guide. PLLs in Stratix IV Devices Figure 5–37 shows a block PFD fbclk February 2011 Altera Corporation ...

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... PLL output clock phase shift. This approach eliminates the need to regenerate a configuration file with the new PLL settings. February 2011 Altera Corporation shows how the VCO frequency gradually decreases when the current Switchover Occurs 5– ...

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... The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, all counters are not updated simultaneously. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices (Note 1) LF/K/CP (3) PFD /C2 /C1 counters. PLLs in Stratix IV Devices VCO /m /C0 /n February 2011 Altera Corporation ...

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... PLL counters have been updated with new settings. 6. Reset the PLL using the areset signal if you make any changes to the post-scale output C counters or to the Icp settings. 7. You can repeat steps 1-5 to reconfigure the PLL any number of times. February 2011 Altera Corporation Source Destination Logic array or I/O pin ...

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... VCO output clock. However and 6 setting for the high- and low-count values, respectively, produces an output clock with a 40% - 60% duty cycle. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices PLLs in Stratix IV Devices (MSB) Dn Dn_old Dn February 2011 Altera Corporation ...

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... PLLs have seven post-scale counters and a 180-bit scan chain. number of bits for each component of a Stratix IV PLL. Table 5–11. Top and Bottom PLL Reprogramming Bits (Part Block Name Charge Pump Current VCO Post-Scale divider (K) February 2011 Altera Corporation Number of Bits Counter C9 (2) 16 ...

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... Figure 5–42. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix IV PLLs DATAOUT 0 1 Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Number of Bits Counter ( — LSB DATAOUT PLLs in Stratix IV Devices Total Other ( — 234 (Note DATAIN rbypass 7 LB rselodd 7 February 2011 Altera Corporation ...

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... Stratix IV PLLs. Table 5–13. Loop-Filter Resistor Bit Settings LFR[ Table 5–14 lists the possible settings for loop-filter capacitor (C) values for Stratix IV PLLs. Table 5–14. Loop-Filter Capacitor Bit Settings LFC[ February 2011 Altera Corporation CP[1] CP[ LFR[3] LFR[2] LFR[ ...

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... Logic array or I/O pin Logic array or I/O pin PLLs in Stratix IV Devices MSB Description 1 (1) PLL counter bypassed PLL counter not bypassed because 0 (1) bit 8 (MSB) is set to 0 Destination PLL reconfiguration circuit PLL reconfiguration circuit PLL reconfiguration circuit February 2011 Altera Corporation ...

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... Wait for PHASEDONE to go high. 6. Repeat steps 1-5 as many times as required to perform multiple phase-shifts. All signals are synchronous to SCANCLK and are latched on the SCANCLK edges and must meet tsu/th requirements with respect to SCANCLK edges. February 2011 Altera Corporation Description Source GCLK, RCLK or I/O pin ...

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... Phase-Locked Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User Guide. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Figure 5–43), the values of PHASEUPDOWN and b c PHASEDONE goes low synchronous with SCANCLK t CONFIGPHASE PLLs in Stratix IV Devices Figure 5–43, this is d February 2011 Altera Corporation ...

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... April 2009 2.2 Updated Figure 5–3 and Figure 5–4. ■ Updated the “Periphery Clock Networks” section. ■ February 2011 Altera Corporation chapter. Changes “Clock Input Connections to the PLLs”,“PLL Clock I/O Modes”, and “Clock Switchover” sections. ...

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... November 2008 2.0 Updated Figure 5–20 ■ Added Figure 5–21 ■ Made minor editorial changes. ■ May 2008 1.0 Initial release. Stratix IV Device Handbook Volume 1 Chapter 5: Clock Networks and PLLs in Stratix IV Devices Changes . . Document Revision History February 2011 Altera Corporation ...

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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. April 2011 Altera Corporation Section II. I/O Interfaces ® IV device I/O features, external ...

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... II–2 Stratix IV Device Handbook Volume 1 Section II: I/O Interfaces Revision History April 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... General purpose PC and embedded system DDR SDRAM DDR2 SDRAM DDR3 SDRAM QDRII/RLDRAM II QDRII/QDRII+/RLDRAM II General purpose DDR SDRAM DDR2 SDRAM DDR3 SDRAM Clock interfaces Chapter 6: I/O Features in Stratix IV Devices I/O Standards Support ) Table 6–1 lists the Application February 2011 Altera Corporation ...

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... SSTL-2 Class II JESD8-9B SSTL-18 Class I JESD8-15 SSTL-18 Class II JESD8-15 SSTL-15 Class I — SSTL-15 Class II — February 2011 Altera Corporation I/O Standard Clock interfaces Clock interfaces High-speed communications Flat panel display Flat panel display Video graphics and clock distribution CCIO 6–19. chapter. ...

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... February 2011 Altera Corporation ...

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... PLL_R[1,4]_clk pins, which support differential input operations only. f For the number of channels available for the LVDS I/O standard, refer to the High-Speed Differential I/O Interface and DPA in Stratix IV Devices information about transceiver-bank-related features, refer to the Architecture in Stratix IV Devices February 2011 Altera Corporation (Note 1) (Part (V) CCIO ...

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... LVPECL, which is supported on clk input pins only. Bank 4C Bank 3C when configured as differential clock inputs. They are powered by V CCCLKIN . CCIO Chapter 6: I/O Features in Stratix IV Devices I/O Banks (8) Bank 7B Bank 7A Bank 4B Bank 4A when configured as CCIO February 2011 Altera Corporation ...

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... Column and row I/O banks support LVPECL standards for input clock operation. (8) Figure 6– top view of the silicon die that corresponds to a reverse view for flip chip packages graphical representation only. February 2011 Altera Corporation (Note 1), (2), (3), (4), (5), (6), (7), Bank 8C Bank 7C I/O banks 7A, 7B & ...

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... This is shown in Figure 6–3. Figure 6–3. Bank Migration Path with Increasing Device Size Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices show the number of I/O pins available in each I/O bank I/O Banks Figure 6–4 48 February 2011 Altera Corporation ...

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... Number of I/Os Bank Name 48 Bank 1A 42 Bank 1C 42 Bank 2C 48 Bank 2A February 2011 Altera Corporation Figure 6–16 show the number of I/O pins and packaging through Figure 6–16, the pin count includes all general purpose I/Os, Bank Name Bank 1A Bank 6A EP4SE230 Bank 1C ...

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... Bank 6A 50 Bank 6B 24 Bank 6C 42 EP4SE530 EP4SE820 Bank 5C 42 Bank 5B 24 Bank 5A 50 Bank Name Number of I/Os Bank 6A 50 Bank 6B 36 Bank 6C 50 EP4SE530 EP4SE820 Bank 5C 50 Bank 5B 36 Bank 5A 50 Bank Name Number of I/Os February 2011 Altera Corporation I/O Banks ...

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... FineLine BGA Package Number of I/ Figure 6–9. Number of I/Os in Each Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package Number of I/Os Number of Transceiver Channels February 2011 Altera Corporation Number of Transceiver Channels Bank Name Bank 1A EP4SGX70 Bank 1C EP4SGX110 EP4SGX180 EP4SGX230 Bank 2C ...

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... EP4SGX110 Name (Note 1), (2) EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 Chapter 6: I/O Features in Stratix IV Devices I/O Banks 32 26 Bank 4* GXBR1 Bank 4* GXBR0 Bank Number of I/Os 48 Bank 6A Bank 6C 42 Bank 4 (2) GXBR1 Bank 4 (2) GXBR0 Bank Name Number of I/Os February 2011 Altera Corporation ...

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... Bank 2A Bank 4 (1) GXBL2 Bank 4 (1) GXBL1 Bank 4 (1) GXBL0 Note to Figure 6–12: (1) There are two additional PMA-only transceiver channels in each transceiver bank. February 2011 Altera Corporation (Note 1) EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530 Bank 6A 48 Bank 6C 42 Bank 5C 42 Bank 5A 48 ...

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... There are two additional PMA-only transceiver channels in each transceiver bank. Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices Bank 6A Bank 6C Bank 5C Bank 5B Bank 5A EP4SGX530 Bank EP4SGX290 4 (1) GXBR3 EP4SGX360 Bank 4 (1) GXBR2 Bank 4 (1) GXBR1 Bank 4 (1) GXBR0 Bank Name Number of I/Os February 2011 Altera Corporation I/O Banks ...

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... Bank 2A Bank 4 (1) GXBL2 Bank 4 (1) GXBL1 Bank 4 (1) GXBL0 Note to Figure 6–14: (1) There are two additional PMA-only transceiver channels in each transceiver bank. February 2011 Altera Corporation Bank 6A 50 Bank 6C 42 Bank 5C 42 EP4SGX290 EP4SGX360 Bank 5A 50 EP4SGX530 Bank 4 (1) GXBR2 ...

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... Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices Figure 6–15 and Figure 6–16 applies to Stratix IV GX and GT Bank 6A Bank 6C Bank 5C EP4S100G3 Bank 5B EP4S100G4 EP4S100G5 Bank 5A Bank GXBR2 Bank GXBR1 Bank GXBR0 I/O Banks (1) 4 (1) 4 (1) Bank Name Number of I/Os February 2011 Altera Corporation ...

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... Programmable output-current strength ■ Programmable slew rate Programmable output delay ■ ■ Programmable bus-hold ■ Programmable pull-up resistor ■ Open-drain output On-chip series termination with calibration ■ February 2011 Altera Corporation Bank 6A 44 Bank 6C 23 Bank 5C 23 EP4S40G2 EP4S40G5 EP4S100G2 Bank 5A 46 EP4S100G5 ...

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... II software. Chapter 6: I/O Features in Stratix IV Devices I/O Structure DQS Logic Block D6_OCT D5_OCT Dynamic OCT Control (2) V CCIO Delay V CCIO PCI Clamp Programmable Pull-Up Resistor From OCT Calibration Block Output Buffer On-Chip Termination Input Buffer Bus-Hold Circuit February 2011 Altera Corporation ...

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... To ensure device reliability and proper operation, when interfacing with a 3.3-V I/O system using Stratix IV devices, ensure that you do not violate the absolute maximum ratings of the devices. Altera recommends performing IBIS simulation to determine that the overshoot and undershoot voltages are within the guidelines. ...

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... Current Strength Current Strength Setting (mA) for Setting (mA) for Column I/O Pins Row I/O Pins 16 16, 12 16 12, 10 12, 10 12, 10 12, 10 12, 10 16, 8 12, 10 16, 8 12, 10 12, 10 12, 10 February 2011 Altera Corporation I/O Structure 12 16 — — ...

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... You can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. 1 Altera recommends performing IBIS or SPICE simulations to determine the best slew rate setting for your specific application. February 2011 Altera Corporation (Note ...

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... Bus-hold circuitry uses a resistor with a nominal resistance ( Ω to weakly pull the signal level to the last-driven state. Stratix IV Device Handbook Volume 1 Chapter 6: I/O Features in Stratix IV Devices chapter. 6–18. The delay chains can independently control the chapter approximately BH February 2011 Altera Corporation I/O Structure Figure 6– ...

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... The output levels are compatible with systems of the same voltage as the power supply. (For example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems.) February 2011 Altera Corporation chapter. level. CCIO chapter ...

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... Stratix (2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3 3.3 V. You have the option to use an internal clamping diode for column I/O pins. (3) Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one V is not supported when ...

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... For the SSTL Class II standard, you must select the 25- Ω on-chip series termination setting (to match the 50- Ω transmission line and the near-end external 50- Ω pull- February 2011 Altera Corporation through an external 25- Ω ±1% or 50- Ω ±1% CCIO through an external 50- Ω ...

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... On-Chip Termination Support and I/O Termination Schemes Figure 6–19 is the intrinsic impedance of the transistors. Calibration Stratix IV Driver Series Termination V CCIO Ω GND On-Chip Series Termination Setting Row I/O (Ω Chapter 6: I/O Features in Stratix IV Devices Receiving Device Column I/O (Ω February 2011 Altera Corporation ...

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... This feature is automatically enabled if you are using a bidirectional I/O with 25-Ω calibrated OCT R f For more information about how to enable the left-shift series termination feature in the ALTIOBUF megafunction, refer to the Guide. February 2011 Altera Corporation On-Chip Series Termination Setting Row I/O (Ω) 50 — 50 ...

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... I/O standards that support on-chip parallel termination On-Chip Parallel Termination Setting (Column I/O) (Ω Chapter 6: I/O Features in Stratix IV Devices Figure 6–20 shows on-chip of the CCIO Stratix IV OCT V CCIO 100 Ω 100 Ω GND Receiver On-Chip Parallel Termination Setting (Row I/O) (Ω February 2011 Altera Corporation ...