EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 239

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–14. Number of DQS/DQ Groups per Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the
1517-Pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 devices do not support × 32/× 36 mode. To interface with a × 36 QDR II+/QDR II SRAM
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a × 4 DQS/DQ group with any of its pin members
February 2011 Altera Corporation
device, refer to
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Make sure that the DQS/DQ groups that you have chosen are not used for configuration as you may lose up to
four × 4 DQS/DQ groups, depending on your configuration scheme.
Figure
I/O Bank 1C
20 User I/Os
21 User I/Os
I/O Bank 2C
I/O Bank 2A
I/O Bank 1A
43 User I/Os
46 User I/Os
7–14:
x16/x18=0
x16/x18=0
x16/x18=1
x16/x18=0
x8/x9=0
x8/x9=0
x8/x9=2
x8/x9=1
x4=0
x4=1
DLL1
x4=6
DLL0
x4=5
“Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
I/O Bank 8A
I/O Bank 3A
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
UP
x4=6
x4=6
and R
(Note
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
I/O Bank 8B
I/O Bank 3B
24 User I/Os
24 User I/Os
EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices
1), (2), (3), (4),
x16/x18=1
x16/x18=1
x8/x9=2
x8/x9=2
x4=4
x4=4
in the 1517-Pin FineLine BGA
I/O Bank 3C
I/O Bank 8C
32 User I/Os
32 User I/Os
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x4=3
x4=3
UP
(5)
and R
DN
32 User I/Os
I/O Bank 4C
32 User I/Os
I/O Bank 7C
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
x4=3
x4=3
I/O Bank 4B
24 User I/Os
24 User I/Os
I/O Bank 7B
x16/x18=1
x16/x18=1
x8/x9=2
x8/x9=2
x4=4
x4=4
I/O Bank 7A
I/O Bank 4A
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
UP
x4=6
x4=6
7–26.
Stratix IV Device Handbook Volume 1
and R
DN
pins for OCT calibration, you
I/O Bank 5C
21 User I/Os
46 User I/Os
I/O Bank 5A
x16/x18=0
I/O Bank 6C
21 User I/Os
I/O Bank 6A
x16/x18=1
44 User I/Os
x16/x18=0
x8/x9=0
x16/x18=0
x8/x9=3
x8/x9=0
x8/x9=1
x4=0
x4=6
DLL2
x4=0
DLL3
x4=5
7–19