EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 215
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–31. LVDS I/O Standard Termination
Notes to
(1)
(2) Side I/O banks support true LVDS output buffers.
(3) Column and side I/O banks support LVDS_E_1R and LVDS_E_3R I/O standards using two single-ended output buffers.
February 2011 Altera Corporation
For LVDS output with a three-resistor network, the R
R
P
value is 120
Figure
with Three-Resistor
External On-Board
with One-Resistor
6–31:
OCT Receive
(Single-Ended
(Single-Ended
OCT Receive
LVDS_E_1R)
OCT Receive
LVDS_E_3R)
LVDS Output
LVDS Output
Termination
(True LVDS
Termination
Network,
Network,
Ω.
Output)
(2)
(3)
(3)
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O interface standard. In Stratix IV devices, the LVDS I/O standard
requires a 2.5-V V
standard in applications requiring high-bandwidth data transfer, such as backplane
drivers and clock distribution. LVDS requires a 100-Ω termination resistor between the
two signals at the input buffer. Stratix IV devices provide an optional 100-Ω
differential termination resistor in the device using on-chip differential termination.
Figure 6–31
available in the row I/O banks.
Differential Outputs
Differential Outputs
Single-Ended Outputs
Single-Ended Outputs
shows LVDS termination. The on-chip differential resistor is only
CCIO
S
and R
(Note 1)
level. The LVDS input buffer requires 2.5-V V
P
values are 120 and 170
External Resistor
≤ 1 inch
≤ 1 inch
External Resistor
Rs
Rs
Rp
Rp
LVDS
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
Ω , respectively. For LVDS output with a one-resistor network, the
100 Ω
100 Ω
100 Ω
100 Ω
Stratix IV Device Handbook Volume 1
Stratix IV OCT
Differential Inputs
Differential Inputs
Differential Inputs
Stratix IV OCT
Stratix IV OCT
Differential Inputs
CCPD
. Use this
6–43
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