EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 18
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–4
Stratix IV Device Handbook Volume 1
Stratix IV E Device
Stratix IV E devices provide an excellent solution for applications that do not require
high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive.
Figure 1–2
Figure 1–2. Stratix IV E Chip View
Note to
(1) Resource counts vary with device selection, package selection, or both.
Figure
shows a high-level Stratix IV E chip view.
1–2:
and Soft-CDR
and Soft-CDR
High-Speed
High-Speed
Purpose
LVDS I/O
with DPA
Purpose
LVDS I/O
with DPA
General
I/O and
General
I/O and
High-Speed LVDS I/O with DPA
PLL
PLL
PLL
PLL
General Purpose I/O and
and Soft-CDR
General Purpose
General Purpose
I/O and Memory
I/O and Memory
Interface
Interface
(Note 1)
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
PLL
PLL
PLL
PLL
General Purpose I/O and
150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
Chapter 1: Overview for the Stratix IV Device Family
General Purpose
General Purpose
I/O and Memory
I/O and Memory
Interface
Interface
February 2011 Altera Corporation
and Soft-CDR
and Soft-CDR
High-Speed
High-Speed
LVDS I/O
LVDS I/O
Purpose
with DPA
Purpose
with DPA
General
I/O and
General
I/O and
PLL
PLL
PLL
PLL
Feature Summary
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