EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 308

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–30
Stratix IV Clocking
Figure 8–23. LVDS/DPA Clocks in the Stratix IV Device Family with Center PLLs
Figure 8–24. LVDS/DPA Clocks in the Stratix IV Device Family with Center and Corner PLLs
Stratix IV Device Handbook Volume 1
2
4
4
2
4
4
4
2
2
4
4
2
2
4
The left and right PLLs feed into the differential transmitter and receive channels
through the LVDS and DPA clock network. The center left and right PLLs can clock
the transmitter and receive channels above and below them. The corner left and right
PLLs can drive I/Os in the banks adjacent to them.
Figure 8–23
information about PLL clocking restrictions, refer to
Guidelines” on page
Figure 8–24
more information about PLL clocking restrictions, refer to
Guidelines” on page
LVDS
Clock
LVDS
Clock
LVDS
LVDS
Clock
Clock
PLL_L2
PLL_L3
Center
Center
PLL_L2
PLL_L3
PLL_L4
Center
Center
Corner
Corner
PLL_L1
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
shows center PLL clocking in the Stratix IV device family. For more
shows center and corner PLL clocking in the Stratix IV device family. For
8–38.
8–38.
Quadrant
Quadrant
Quadrant
Quadrant
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Quadrant
Quadrant
Quadrant
Quadrant
“Differential Pin Placement
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
PLL_R1
PLL_R2
PLL_R3
PLL_R2
PLL_R3
PLL_R4
“Differential Pin Placement
Corner
Center
Center
Corner
Center
Center
February 2011 Altera Corporation
LVDS
Clock
LVDS
Clock
LVDS
Clock
LVDS
Clock
4
4
4
2
2
4
2
2
4
4
2
4
2
4
Stratix IV Clocking