EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 412

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

11–6
Error Detection Block
Stratix IV Device Handbook Volume 1
1
You can enable the Stratix IV device error detection block in the Quartus II software
(refer to
calculate the 16-bit CRC signature for the configuration CRAM bits in the device.
The CRC circuit continues running even if an error occurs. When a soft error occurs,
the device sets the CRC_ERROR pin high. Two types of CRC detection checks the
configuration bits:
■
■
The
in user mode.
CRAM error checking ability (16-bit CRC), which occurs during user mode to be
used by the CRC_ERROR pin.
■
■
■
■
■
16-bit CRC that is embedded in every configuration data frame.
■
■
“Error Detection Block”
For each frame of data, the pre-calculated 16-bit CRC enters the CRC circuit at
the end of the frame data and determines whether there is an error or not.
If an error occurs, the search engine starts to find the location of the error.
The error messages are shifted out through the JTAG instruction or core
interface logics while the error detection block continues running.
The JTAG interface reads out the 16-bit CRC result for the first frame and also
shifts the 16-bit CRC bits to the 16-bit CRC storage registers for test purposes.
Single error, double errors, or double-errors adjacent to each other are
deliberately introduced to configuration memory for testing and design
verification.
During configuration, after a frame of data is loaded into the Stratix IV device,
the pre-computed CRC is shifted into the CRC circuitry.
At the same time, the CRC value for the data frame shifted-in is calculated. If
the pre-computed CRC and calculated CRC values do not match, nSTATUS is set
low. Every data frame has a 16-bit CRC; therefore, there are many 16-bit CRC
values for the whole configuration bitstream. Every device has different
lengths of configuration data frame.
“Software Support” on page
section describes the 16-bit CRC only when the device is
11–10). This block contains the logic necessary to
Chapter 11: SEU Mitigation in Stratix IV Devices
February 2011 Altera Corporation
Error Detection Block