EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 262

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–42
Stratix IV Device Handbook Volume 1
Phase Offset Control
f
There are eight different frequency modes for the Stratix IV DLL, as listed in
Table
frequency mode 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to
implement the phase-shift delay. In frequency modes 4, 5, 6, and 7, only 5 bits of the
DQS delay settings vary with PVT to implement the phase-shift delay; the most
significant bit of the DQS delay setting is set to 0.
Table 7–18. Stratix IV DLL Frequency Modes
For the frequency range of each mode, refer to the
Stratix IV Devices
For 0° shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The
Quartus II software automatically sets the DQ input delay chains so that the skew
between the DQ and DQS/CQ pin at the DQ IOE registers is negligible when 0° shift
is implemented. You can feed the DQS delay settings to the DQS logic block and logic
array.
The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the
DQ pins. The signal can also go into the logic array for resynchronization if you are
not using IOE resynchronization registers. The shifted CQn signal can only go to the
negative-edge input register in the DQ IOE and is only used for QDR II+ and QDR II
SRAM interfaces.
Each DLL has two phase-offset modules and can provide two separate DQS delay
settings with independent offsets, one for the top and bottom I/O bank and one for
the left and right I/O bank, so you can fine-tune the DQS phase-shift settings between
two different sides of the device. Even though you have independent phase offset
control, the frequency of the interface using the same DLL must be the same. Use the
phase offset control module for making small shifts to the input signal and use the
DQS phase-shift circuitry for larger signal shifts. For example, if the DLL only offers a
multiple of 30° phase shift, but your interface needs a 67.5° phase shift on the DQS
signal, you can use two delay chains in the DQS logic blocks to give you 60° phase
shift and use the phase offset control feature to implement the extra 7.5° phase shift.
7–18. Each frequency mode provides different phase shift selections. In
Frequency Mode
0
1
2
3
4
5
6
7
chapter.
Available Phase Shift
22.5, 45, 67.5, 90
60, 120, 180, 240
36, 72, 108, 144
45, 90, 135, 180
36, 72, 108, 144
45, 90, 135, 180
30, 60, 90, 120
30, 60, 90, 120
Chapter 7: External Memory Interfaces in Stratix IV Devices
DC and Switching Characteristics for
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
Number of Delay Chains
16
12
10
12
10
8
8
6