EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 232
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
- Current page: 232 of 432
- Download datasheet (11Mb)
7–12
Figure 7–7. Number of DQS/DQ Groups per Bank in EP4SGX70 and EP4SGX110 Devices with 24 Transceivers in the
1152-Pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX70 and EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
Stratix IV Device Handbook Volume 1
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
7–7:
26 User I/Os (5)
26 User I/Os (5)
I/O Bank 1A (3)
I/O Bank 1C (4)
I/O Bank 1C (4)
32 User I/Os
32 User I/Os
x16/x18=0
x16/x18=0
x16/x18=1
x16/x18=1
x8/x9=1
x8/x9=1
x8/x9=2
x8/x9=2
DLL0
DLL1
x4=3
x4=3
x4=4
x4=4
UP
and R
I/O Bank 8A (3)
I/O Bank 3A (3)
(Note
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
DN
x8/x9=3
x8/x9=3
x4=6
x4=6
pins for OCT calibration. If two pins of a ×4 group are used as R
1), (2), (3), (4),
24 User I/Os
EP4SGX70 and EP4SGX110 Devices
I/O Bank 8C
x16/x18=0
I/O Bank 3C
x8/x9=1
24 User I/Os
x16/x18=0
x4=2
x8/x9=1
in the 1152-Pin FineLine BGA
x4=2
(with 24 Transceivers)
UP
(5)
and R
DN
24 User I/Os
I/O Bank 7C
x16/x18=0
24 User I/Os
I/O Bank 4C
x16/x18=0
x8/x9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
x8/x9=1
x4=3
x4=3
7–26.
Chapter 7: External Memory Interfaces in Stratix IV Devices
I/O Bank 7A (3)
I/O Bank 4A (3)
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
x4=6
x4=6
UP
and R
February 2011 Altera Corporation
26 User I/Os (5)
26 User I/Os (5)
I/O Bank 6A (3)
I/O Bank 6A (3)
I/O Bank 6C
I/O Bank 6C
32 User I/Os
32 User I/Os
x16/x18=0
x16/x18=0
x16/x18=1
x16/x18=1
x8/x9=1
x8/x9=1
Memory Interfaces Pin Support
DN
x8/x9=2
x8/x9=2
DLL3
x4=3
x4=3
DLL2
x4=4
x4=4
pins for OCT calibration, you
“Combining
Related parts for EP4SGX530HH35C2N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: