EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 77

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
February 2011 Altera Corporation
Figure 3–20
behavior for don’t care mode in MLABs.
Figure 3–20. MLABs Mixed-Port Read-During-Write: Don’t Care Mode
Figure 3–21
behavior for old data mode in M9K and M144K blocks.
Figure 3–21. M9K and M144K Blocks Mixed-Port Read-During Write: Old Data Mode
q_b(registered)
q_b_(asyn)
address_a
address_b
wraddress
rdaddress
clk_a&b
bytenna
byteena_a
data_a
wrena
rdenb
data_in
clk_a
wrena
shows a sample functional waveform of mixed-port read-during-write
shows a sample functional waveform of mixed-port read-during-write
AAAA
11
AAAA
11
A0 (old data)
A0
A0
AAAA
BBBB
01
BBBB
01
A0
A0
AAAA
AABB
CCCC
10
CCCC
10
CCBB
AABB
DDDD
11
DDDD
A1(old data)
11
DDDD
EEEE
A1
A1
Stratix IV Device Handbook Volume 1
01
EEEE
A1
A1
DDEE
FFFF
DDDD
10
FFFF
FFEE
EEEE
3–21