EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 429

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 13: Power Management in Stratix IV Devices
Temperature Sensing Diode
April 2011 Altera Corporation
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The TSD is a very sensitive circuit that can be influenced by noise coupled from other
traces on the board and possibly within the device package itself, depending on your
device usage. The interfacing device registers’ temperature is based on millivolts
(mV) of difference, as seen at the external TSD pins. Switching the I/O near the TSD
pins can affect the temperature reading. Altera recommends taking temperature
readings during periods of inactivity in the device or use the internal TSD with
built-in ADC circuitry.
The following are board connection guidelines for the TSD external pin connections:
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For device specification and connection guidelines, refer to the external temperature
sensor device data sheet from the device manufacturer.
The maximum trace lengths for the TEMPDIODE
less than eight inches.
Route both traces in parallel and place them close to each other with grounded
guard tracks on each side.
Altera recommends 10-mils width and space for both traces.
Route traces through a minimum number of vias and crossunders to minimize the
thermocouple effects.
Ensure that the number of vias are the same on both traces.
Ensure both traces are approximately the same length.
Avoid coupling with toggling signals (for example, clocks and I/O) by having the
GND plane between the diode traces and the high frequency signals.
For high-frequency noise filtering, place an external capacitor (close to the external
chip) between the TEMPDIODE
For Maxim devices, use an external capacitor between 2200 pF to 3300 pF.
Place a 0.1 uF bypass capacitor close to the external device.
You can use internal TSD with built-in ADC circuitry and external TSD at the
same time.
If you only use internal ADC circuitry, the external TSD pins
(TEMPDIODE
external TSD pins are not used.
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For more information about the TEMPDIODE
connection when you are not using an external TSD, refer to the
Stratix IV GX and Stratix IV E Pin Connection
P
/TEMPDIODE
N
) can connect these pins to GND because the
P
/TEMPDIODE
N
P
trace.
/TEMPDIODE
Guidelines.
P
/TEMPDIODE
Stratix IV Device Handbook Volume 1
N
traces must be
N
pin
13–5