EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 92

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–12
Table 4–3. Input Register Modes
Stratix IV Device Handbook Volume 1
Parallel input
Shift register input
Loopback input
Notes to
(1) Multiplier operand input wordlengths are statically configured at compile time.
(2) Available only on the A-operand.
(3) Only one loopback input is allowed per half block. For more information, refer to
Register Input Mode
Table
Multiplier and First-Stage Adder
4–3:
(3)
(2)
Shift registers are useful in DSP functions such as FIR filters. When implementing
18 × 18 or smaller width multipliers, you do not need external logic to create the shift
register chain because the input shift registers are internal to the DSP block. This
implementation significantly reduces the logical element (LE) resources required,
avoids routing congestion, and results in predictable timing.
The first multiplier in every half DSP block (top- and bottom-half) in Stratix IV
devices has a multiplexer for the first multiplier B-input (lower-leg input) register to
select between general routing and loopback, as shown in
loopback mode, the most significant 18-bit registered outputs are connected as
feedback to the multiplier input of the first top multiplier in each half DSP block.
Loopback modes are used by recursive filters where the previous output is needed to
compute the current output.
Loopback mode is described in
Table 4–3
The multiplier stage natively supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers.
Other wordlengths are padded up to the nearest appropriate native wordlength; for
example, 16 × 16 would be padded up to use 18 × 18. For more information, refer to
“Independent Multiplier Modes” on page
multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic
signals, signa and signb, control the representation of each operand, respectively. A
logic 1 value on the signa/signb signal indicates that data A/data B is a signed
number; a logic 0 value indicates an unsigned number.
multiplication result for the various operand sign representations. The result of the
multiplication is signed if any one of the operands is a signed value.
Table 4–4. Multiplier Sign Representation
(1)
Data A (signa Value)
Unsigned (logic 0)
Unsigned (logic 0)
lists input register modes for the DSP block.
Signed (logic 1)
Signed (logic 1)
9 × 9
v
—
—
12 × 12
“Two-Multiplier Adder Sum Mode” on page
v
—
—
Data B (signb Value)
Unsigned (logic 0)
Unsigned (logic 0)
Figure 4–15 on page
Signed (logic 1)
Signed (logic 1)
4–15. Depending on the data width of the
18 × 18
v
v
v
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
4–24.
Table 4–4
Figure 4–6 on page
36 × 36
February 2011 Altera Corporation
v
—
—
lists the sign of the
Unsigned
Result
Signed
Signed
Signed
Double
4–22.
v
—
—
4–9. In