EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 195

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
February 2011 Altera Corporation
Programmable Pull-Up Resistor
Programmable Pre-Emphasis
Programmable Differential Output Voltage
MultiVolt I/O Interface
f
f
f
1
For more information about the specific sustaining current driven through this
resistor and the overdrive current used to identify the next-driven input level, refer to
the
Bus-hold circuitry is active only after configuration. When going into user mode, the
bus-hold circuit captures the value on the pin present at the end of configuration.
Each Stratix IV device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 K ) weakly holds the I/O to the V
Programmable pull-up resistors are only supported on user I/O pins and are not
supported on dedicated configuration pins, JTAG pins, or dedicated clock pins. If you
enable the programmable pull-up option, you cannot use the bus-hold feature.
When the optional DEV_OE signal drives low, all the I/O pins remain tri-stated even
with the programmable pull-up option enabled.
Stratix IV LVDS transmitters support programmable pre-emphasis to compensate for
the frequency dependent attenuation of the transmission line. The Quartus II software
allows four settings for programmable pre-emphasis.
For more information about programmable pre-emphasis, refer to the
Differential I/O Interfaces and DPA in Stratix IV Devices
Stratix IV LVDS transmitters support programmable V
settings allow you to adjust output eye height to optimize trace length and power
consumption. A higher V
smaller V
settings for programmable V
For more information about programmable V
Interfaces and DPA in Stratix IV Devices
The Stratix IV architecture supports the MultiVolt I/O interface feature that allows the
Stratix IV devices in all packages to interface with systems of different supply
voltages.
You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, or 3.0-V power supply,
depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when VCCIO pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems.)
DC and Switching Characteristics for Stratix IV Devices
OD
swing reduces power consumption. The Quartus II software allows four
OD
swing improves voltage margins at the receiver end; a
OD
.
chapter.
OD
CCIO
, refer to the
level.
chapter.
OD
chapter.
. The programmable V
Stratix IV Device Handbook Volume 1
High-Speed Differential I/O
High-Speed
OD
6–23