EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 156

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–40
Stratix IV Device Handbook Volume 1
In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the
status of the two clock inputs. When they are asserted, the clock sense block has
detected that the corresponding clock input has stopped toggling. These two signals
are not valid if the frequency difference between inclk0 and inclk1 is greater than
20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is
being selected as the reference clock to the PLL. When the frequency difference
between the two clock inputs is more than 20%, the activeclock signal is the only
valid status signal.
Figure 5–35
automatic switchover mode. In this example, the inclk0 signal is stuck low. After the
inclk0 signal is stuck at low for approximately two clock cycles, the clock sense
circuitry drives the clkbad[0] signal high. Also, because the reference clock signal is
not toggling, the switchover state machine controls the multiplexer through the
clkswitch signal to switch to the backup clock, inclk1.
Figure 5–35. Automatic Switchover After Loss of Clock Detection
Note to
(1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure,
Manual Override
In automatic switchover with manual override mode, you can use the clkswitch
input for user- or system-controlled switch conditions. You can use this mode for
same-frequency switchover, or to switch between inputs of different frequencies. For
example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover
using clkswitch because the automatic clock-sense circuitry cannot monitor clock
input (inclk0 and inclk1) frequencies with a frequency difference of more than 100%
(2×). This feature is useful when the clock sources originate from multiple cards on the
backplane, requiring a system-controlled switchover between the frequencies of
operation. You must choose the backup clock frequency and set the m, n, c, and k
counters accordingly so the VCO operates within the recommended operating
frequency range of 600 to 1,600 MHz. The ALTPLL MegaWizard Plug-in Manager
notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this
requirement.
switchover is enabled on the falling edge of inclk1.
Figure
5–35:
shows an example waveform of the switchover feature when using
activeclock
clkbad0
clkbad1
muxout
inclk0
inclk1
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
(1)
February 2011 Altera Corporation
PLLs in Stratix IV Devices