EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 377

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device Configuration Pins
Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 2 of 4)
April 2011 Altera Corporation
MSEL[2..0]
nCONFIG
nSTATUS
Pin Name
User Mode
N/A
N/A
N/A
Configuration
Scheme
All
All
All
Bidirectional
open-drain
Pin Type
Input
Input
Three-bit configuration input that sets the Stratix IV device
configuration scheme. For the appropriate connections,
refer to
You must hardwire these pins to V
The MSEL[2..0] pins have internal 5-kΩ pull-down
resistors that are always active.
Configuration control input. Pulling this pin low during
user-mode causes the device to lose its configuration data,
enter a reset state, and tri-state all I/O pins. Returning this
pin to a logic high level initiates a reconfiguration.
Configuration is possible only if this pin is high, except in
JTAG programming mode, when nCONFIG is ignored.
The device drives nSTATUS low immediately after power-up
and releases it after the POR time.
During user mode and regular configuration, this pin is
pulled high by an external 10-kΩ resistor.
This pin, when driven low by the Stratix IV device, indicates
that the device has encountered an error during
configuration.
■
■
Driving nSTATUS low after configuration and initialization
does not affect the configured device. If you use a
configuration device, driving nSTATUS low causes the
configuration device to attempt to configure the device, but
because the device ignores transitions on nSTATUS in user
mode, the device does not reconfigure. To initiate a
reconfiguration, nCONFIG must be pulled low.
If you have enabled the Auto-restart configuration after
error option, the nSTATUS pin transitions from high to low
and back again to high when a configuration error is
detected. This appears as a low pulse at the pin with a
minimum pulse width of 10 μs to a maximum pulse width
of 500 μs, as defined in the t
Status output—If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input—If an external source drives the nSTATUS
pin low during configuration or initialization, the target
device enters an error state.
Table 10–1 on page
Description
10–2.
STATUS
Stratix IV Device Handbook Volume 1
CCPGM
specification.
or GND.
10–43