EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 277

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Stratix IV Devices
Document Revision History
Table 7–21. Document Revision History (Part 2 of 2)
February 2011 Altera Corporation
November 2009
June 2009
April 2009
March 2009
November 2008
May 2008
Date
Version
3.0
2.0
2.3
2.2
2.1
1.0
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Initial release.
Updated the “Memory Interfaces Pin Support” and “Combining ×16/×18 DQS/DQ Groups
for a ×36 QDR II+/QDR II SRAM Interface” sections.
Updated Table 7–1, Table 7–2, Table 7–7, and Table 7–12.
Updated Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6, Figure 7–7, Figure 7–8,
Figure 7–9, Figure 7–10, Figure 7–11, Figure 7–13, Figure 7–14, Figure 7–15, and
Figure 7–16.
Added Figure 7–12 and Figure 7–17.
Added Table 7–14, Table 7–17, Table 7–19, and Table 7–20.
Added “Delay Chain” and “I/O Configuration Block and DQS Configuration Block”
sections.
Removed Figure 7-8 and Figure 7-12.
Removed Table 7-1, Table 7-2, and Table 7-24.
Minor text edits.
Updated “Overview” and “Leveling Circuitry”.
Updated Figure 7–26 and Figure 7–27.
Updated Table 7–3.
Added introductory sentences to improve search ability.
Removed the Conclusion section.
Updated Table 7–5, Table 7–6, Table 7–15, and Table 7–17
Removed Figure 7-12, Figure 7-13, and Figure 7-20
Updated Table 7–1, Table 7–5, Table 7–8, Table 7–12, Table 7–13, Table 7–14,
Table 7–15, and Table 7–17.
Replaced Table 7–6.
Added Table 7–11 and Table 7–16.
Updated Figure 7–3, Figure 7–6, Figure 7–8, Figure 7–9, and Figure 7–11.
Added Figure 7–7, Figure 7–11, Figure 7–12, Figure 7–13, and Figure 7–20.
Updated “Combining ×16/×18 DQS/DQ Groups for ×36 QDR II+/QDR II SRAM Interface”.
Updated “Rules to Combine Groups”.
Removed “Referenced Documents” section.
Updated Table 7–1, Table 7–2, Table 7–3, Table 7–4, Table 7–5, and Table 7–6.
Added Table 7–7.
Updated Figure 7–1 and Figure 7–19.
Updated “Combining ×16/×18 DQS/DQ groups for ×36 QDR II+/QDR II SRAM Interface”
on page 7–26.
Updated “Rules to Combine Groups” on page 7–27.
Updated “DQS Phase-Shift Circuitry” on page 7–29.
Updated Table 7–9, Table 7–10, Table 7–11, Table 7–13, Table 7–13, Table 7–14,
Table 7–15, Table 7–15, Table 7–16, and Table 7–18.
Updated Figure 7–30 and Figure 7–31.
Made minor editorial changes.
Changes
Stratix IV Device Handbook Volume 1
7–57