EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 340

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–6
Fast Passive Parallel Configuration
Stratix IV Device Handbook Volume 1
FPP Configuration Using a MAX II Device as an External Host
1
Fast passive parallel configuration in Stratix IV devices is designed to meet the
continuously increasing demand for faster configuration times. Stratix IV devices are
designed with the capability of receiving byte-wide configuration data per clock
cycle.
You can perform FPP configuration of Stratix IV devices using an intelligent host,
such as a MAX II device or a microprocessor.
FPP configuration using compression and an external host provides the fastest
method to configure Stratix IV devices. In this configuration scheme, you can use a
MAX II device as an intelligent host that controls the transfer of configuration data
from a storage device, such as flash memory, to the target Stratix IV device. You can
store configuration data in .rbf, .hex, or .ttf format. When using the MAX II device as
an intelligent host, a design that controls the configuration process, such as fetching
the data from flash memory and sending it to the device, must be stored in the MAX II
device.
If you are using the Stratix IV decompression and/or design security features, the
external host must be able to send a DCLK frequency that is ×4 the data rate.
The ×4 DCLK signal does not require an additional pin and is sent on the DCLK pin. The
maximum DCLK frequency is 125 MHz, which results in a maximum data rate of
250 Mbps. If you are not using the Stratix IV decompression or design security
features, the data rate is ×8 the DCLK frequency.
Figure 10–1
device and a MAX II device for single device configuration.
Figure 10–1. Single Device FPP Configuration Using an External Host
Note to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V
high enough to meet the V
up all configuration system I/Os with V
Figure
10–1:
shows the configuration interface connections between the Stratix IV
(MAX II Device or
Microprocessor)
External Host
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
ADDR DATA[7..0]
Memory
IH
specification of the I/O on the device and the external host. Altera recommends powering
CCPGM.
10 kΩ
V
CCPGM
(1)
V
CCPGM
10 kΩ
GND
(1)
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix IV Device
Fast Passive Parallel Configuration
MSEL[2..0]
April 2011 Altera Corporation
nCEO
GND
N.C.
CCPGM
must be