EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 135

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Table 5–7. PLL Availability for Stratix IV Devices (Part 1 of 2)
February 2011 Altera Corporation
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
EP4SE230
EP4SE360
EP4SE530
Device
Cascading PLLs
f
f
Package
1
F1517
H1517
F1517
F1932
F1932
H1517
F1932
H1152
H1517
F1152
F1760
H780
F780
You can cascade the left/right and top/bottom PLLs through the GCLK and RCLK
networks. In addition, where two left/right or top/bottom PLLs exist next to each
other, there is a direct connection between them that does not require the GCLK or
RCLK network. Using this path reduces clock jitter when cascading PLLs.
Stratix IV GX devices allow cascading the left and right PLLs to transceiver PLLs
(CMU PLLs and receiver CDRs).
For more information, refer to the “FPGA Fabric PLLs -Transceiver PLLs Cascading”
section in the
When cascading PLLs in Stratix IV devices, the source (upstream) PLL must have a
low-bandwidth setting while the destination (downstream) PLL must have a
high-bandwidth setting. Ensure that there is no overlap of the bandwidth ranges of
the two PLLs.
For more information about PLL cascading in external memory interfaces designs,
refer to the
Guide.
Stratix IV devices offer up to 12 PLLs that provide robust clock management and
synthesis for device clock management, external system clock management, and
high-speed I/O interfaces. The nomenclature for the PLLs follows their geographical
location in the device floor plan. The PLLs that reside on the top and bottom sides of
the device are named PLL_T1, PLL_T2, PLL_B1 and PLL_B2; the PLLs that reside on the
left and right sides of the device are named PLL_L1, PLL_L2, PLL_L3, PLL_L4, PLL_R1,
PLL_R2, PLL_R3, and PLL_R4.
Table 5–7
v
v
v
v
v
L1
—
—
—
—
—
—
—
—
lists the number of PLLs available in the Stratix IV device family.
v
v
v
v
v
v
v
v
L2
v
v
v
v
v
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User
Transceiver Clocking in Stratix IV Devices
L3
v
v
v
v
v
v
v
—
v
v
v
v
—
v
v
v
v
v
L4
—
—
—
—
—
—
—
—
v
v
v
v
v
v
v
v
v
v
v
v
v
T1
v
v
v
v
v
v
v
v
v
v
v
T2
—
—
B1
v
v
v
v
v
v
v
v
v
v
v
v
v
B2
v
v
v
v
v
v
v
v
v
v
v
—
—
chapter.
Stratix IV Device Handbook Volume 1
R1
—
—
—
v
v
—
v
—
—
—
—
v
v
R2
v
v
v
v
v
v
v
v
v
v
v
v
v
R3
v
v
v
v
v
v
v
v
v
v
v
—
—
R4
v
v
v
v
v
—
—
—
—
—
—
—
—
5–19