EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 352

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–18
Stratix IV Device Handbook Volume 1
In fast AS configuration schemes, Stratix IV devices drive out control signals on the
falling edge of DCLK. The serial configuration device responds to the instructions by
driving out configuration data on the falling edge of DCLK. Then the data is latched
into the Stratix IV device on the following falling edge of DCLK.
In configuration mode, Stratix IV devices enable the serial configuration device by
driving the nCSO output pin low, which connects to the chip select (nCS) pin of the
configuration device. The Stratix IV device uses the serial clock (DCLK) and serial data
output (ASDO) pins to send operation commands and/or read address signals to the
serial configuration device. The configuration device provides data on its serial data
output (DATA) pin, which connects to the DATA0 input of the Stratix IV devices.
After all the configuration bits are received by the Stratix IV device, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ resistor.
Initialization begins only after the CONF_DONE signal reaches a logic high level. All AS
configuration pins (DATA0, DCLK, nCSO, and ASDO) have weak internal pull-up resistors
that are always active. After configuration, these pins are set as input tri-stated and
are driven high by the weak internal pull-up resistors. The CONF_DONE pin must have
an external 10-kΩ pull-up resistor in order for the device to initialize.
In Stratix IV devices, the initialization clock source is either the internal oscillator or
the optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Stratix IV device provides itself
with enough clock cycles for proper initialization. You also have the flexibility to
synchronize initialization of multiple devices or to delay initialization with the CLKUSR
option. You can turn on the Enable user-supplied start-up clock (CLKUSR) option in
the Quartus II software from the General tab of the Device and Pin Options dialog
box. When you select the Enable user supplied start-up clock option, the CLKUSR pin
is the initialization clock source. Supplying a clock on CLKUSR does not affect the
configuration process. After all configuration data is accepted and CONF_DONE goes
high, CLKUSR is enabled after four clock cycles of DCLK. After this time period elapses,
Stratix IV devices require 8,532 clock cycles to initialize properly and enter user mode.
Stratix IV devices support a CLKUSR f
An optional INIT_DONE pin is available, which signals the end of initialization and the
start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high. This
low-to-high transition signals that the device has entered user mode. When
initialization is complete, the device enters user mode. In user mode, the user I/O
pins no longer have weak pull-up resistors and function as assigned in your design.
If an error occurs during configuration, Stratix IV devices assert the nSTATUS signal
low, indicating a data frame error, and the CONF_DONE signal stays low. If the
Auto-restart configuration after error option (available in the Quartus II software
from the General tab of the Device and Pin Options dialog box) is turned on, the
Stratix IV device resets the configuration device by pulsing nCSO, releases nSTATUS
after a reset time-out period (a maximum of 500 µs), and retries configuration. If this
option is turned off, the system must monitor nSTATUS for errors and then pulse
nCONFIG low for at least 2 μs to restart configuration.
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
MAX
of 125 MHz.
Fast Active Serial Configuration (Serial Configuration Devices)
April 2011 Altera Corporation