EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 346

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–12
Figure 10–4. FPP Configuration Timing Waveform
Notes to
(1) Use this timing waveform when you have not enabled the decompression and design security features.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(3) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins
Table 10–4. FPP Timing Parameters for Stratix IV Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 1
t
t
t
t
t
t
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
When nCONFIG is pulled low, a reconfiguration cycle begins.
depends on the dual-purpose pin settings.
Figure
nCONFIG low to CONF_DONE
low
nCONFIG low to nSTATUS
low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS
high
nCONFIG high to first rising
edge on DCLK
10–4:
CONF_DONE (4)
Parameter
nSTATUS (3)
INIT_DONE
DATA[7..0]
nCONFIG
FPP Configuration Timing
Figure 10–4
MAX II device as an external host. This waveform shows the timing when you have
not enabled the decompression and design security features.
Table 10–4
when you have not enabled the decompression and design security features.
User I/O
DCLK
t
t
CF2CD
CFG
lists the timing parameters for Stratix IV devices for an FPP configuration
t
CF2ST1
shows the timing waveform for an FPP configuration when using a
t
CF2ST0
t
t
CF2CK
ST2CK
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Stratix IV
t
Byte 0 Byte 1 Byte 2 Byte 3
STATUS
High-Z
t
CH
t
(7)
CLK
t
DSU
t
CL
t
DH
(Note
Minimum
Stratix IV
500
—
—
10
—
(8)
1),
2
(2)
Stratix IV
Byte n-2 Byte n-1
(9)
(Note
Byte n
1),
Stratix IV
t
CD2UM
(7)
(2)
(6)
Maximum
Stratix IV
500
500
Fast Passive Parallel Configuration
User Mode
User Mode
800
800
(8)
—
—
April 2011 Altera Corporation
(5)
(3)
(4)
Stratix IV
(9)
Units
μs
μs
μs
μs
ns
ns