EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 419

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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SIV51012-3.2
BST Architecture
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51012-3.2
f
The IEEE Std. 1149.1 boundary-scan test (BST) circuitry available in Stratix
devices provides a cost-effective and efficient way to test systems that contain devices
with tight lead spacing. Circuit boards with Altera and other IEEE Std.
1149.1-compliant devices can use EXTEST, SAMPLE/PRELOAD, and BYPASS modes to
create serial patterns that internally test the pin connections between devices and
check device operation.
This chapter describes how to use the IEEE Std. 1149.1 BST circuitry in Stratix IV
devices. The features are similar to Stratix III devices, unless stated otherwise in this
chapter.
This chapter contains the following sections:
■
■
■
■
■
A device operating in IEEE Std. 1149.1 BST mode uses four required pins, TDI, TDO,
TMS, TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down
resistor, while the TDI, TMS, and TRST pins have internal weak pull-up resistors. The
TDO output pin and all the JTAG input pins are powered by the 2.5-V/3.0-V V
supply of I/O bank 1A. All user I/O pins are tri-stated during JTAG configuration.
For more information about the description and functionality of all JTAG pins,
registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)
controller, refer to the
chapter in volume 1 of the Stratix III Device Handbook.
“BST Architecture”
“BST Operation Control” on page 12–2
“I/O Voltage Support in a JTAG Chain” on page 12–4
“BST Circuitry” on page 12–4
“BSDL Support” on page 12–4
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
12. JTAG Boundary-Scan Testing in
Stratix IV Devices
®
IV
CCPD
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