EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 336

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–2
Configuration Schemes
Table 10–1. Configuration Schemes for Stratix IV Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 1
Fast passive parallel
Passive serial
Fast AS (40 MHz)
Remote system upgrade fast AS (40 MHz)
FPP with design security feature and/or decompression enabled
Configuration Devices
f
1
1
(1)
Configuration Scheme
■
■
■
■
Altera
configuration solution for Stratix IV devices and are used in the fast AS configuration
scheme. Serial configuration devices offer a low-cost, low pin-count configuration
solution.
For information about serial configuration devices, refer to the
Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Configuration Handbook.
All minimum timing information in this chapter covers the entire Stratix IV family.
Some devices may work at less than the minimum timing stated in this handbook due
to process variation.
Select the configuration scheme by driving the Stratix IV device MSEL pins either high
or low, as shown in
supply. Altera recommends hard wiring the MSEL[] pins to V
MSEL[2..0] pins have 5-kΩ internal pull-down resistors that are always active.
During power-on reset (POR) and during reconfiguration, the MSEL pins must be at
V
To avoid problems with detecting an incorrect configuration scheme, hardwire the
MSEL[] pins to V
the MSEL[] pins by a microprocessor or another device.
IL
“Remote System Upgrade Mode” on page 10–53
“Dedicated Remote System Upgrade Circuitry” on page 10–56
“Quartus II Software Support” on page 10–62
“Design Security” on page 10–63
and V
®
serial configuration devices support a single-device and multi-device
IH
levels of V
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
CCPGM
(1)
Table
CCPGM
and GND without pull-up or pull-down resistors. Do not drive
10–1. The MSEL input buffers are powered by the V
voltage to be considered logic low and logic high.
(2)
MSEL2
0
0
0
0
0
MSEL1
CCPGM
0
1
1
1
0
Serial Configuration
April 2011 Altera Corporation
in volume 2 of the
and GND. The
Configuration Schemes
MSEL0
CC
0
0
1
1
1
power